公开(公告)号：US20160035682A1

公开(公告)日：2016-02-04

申请号：US14881365

申请日：2015-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

Abstract translation: 由深沟槽电容器引起的晶片弯曲由晶片背面形成的结构改善。 反面的结构包括拉伸膜。 膜可以形成在晶片背面的沟槽内，这增强了它们的作用。 在一些实施例中，晶片用于形成3D-IC器件。 在一些实施例中，3D-IC器件包括高电压或高功率电路。

公开(公告)号：US20150311300A1

公开(公告)日：2015-10-29

申请号：US14261539

申请日：2014-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/02271 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42332

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.

Abstract translation: 本公开的一些实施例涉及用于形成快闪存储器的方法。 在该方法中，在半导体衬底上形成隧道氧化物。 在隧道氧化物上形成一层硅点成核。 硅点层包括具有根据第一尺寸分布而不同的各自的初始尺寸的硅点成核。 进行蚀刻处理以减小硅点成核的初始尺寸，因此尺寸减小的硅点成核具有根据第二尺寸分布而不同的相应减小的尺寸。 第二尺寸分布具有比第一尺寸分布更小的扩展。

公开(公告)号：US20150054055A1

公开(公告)日：2015-02-26

申请号：US13974137

申请日：2013-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsung-Yu Chen ,  Cheng-Te Lee ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L29/792 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/02118 ,  H01L21/28273 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/8239 ,  H01L27/11521 ,  H01L27/11565 ,  H01L29/0665 ,  H01L29/0692 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/792 ,  Y10S977/774

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer.

Abstract translation: 本公开的一些实施例涉及实现存储器单元内的离散存储元件的基本上均匀的图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在基材的表面上，并进行自组装成相分离的材料，该相分离材料包含第二聚合物物质的规则形式的第二聚合物种类的聚合物基质， 第一种聚合物种类。 然后除去聚合物基质中的第二种聚合物物质，形成孔。 然后通过孔进行蚀刻，利用聚合物基质作为硬掩模，以在设置在衬底表面上的种子层上的电介质层中形成基本上相同的孔的图案。 然后将种子层上的外延沉积物用于在介电层内生长基本上均匀的离散存储元件图案。

公开(公告)号：US20140374880A1

公开(公告)日：2014-12-25

申请号：US13925984

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10829 ,  H01L24/73 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/91 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.

Abstract translation: 本公开涉及一种形成电容器结构的方法，包括在凹槽的底部和侧壁上沉积由多个氧化物/氮化物/氧化物（ONO）层隔开的多个均匀厚度的多个第一多晶硅（POLY）层，以及 基材表面。 第二POLY层沉积在多个第一POLY层上，被ONO层隔开，并填充凹槽的其余部分。 用第一化学机械抛光（CMP）去除第二POLY层和第二ONO层的部分。 多个第一POLY层和表面上不在电容器结构的掺杂区域内的第一ONO层的一部分用第一图案和蚀刻工艺去除，使得多个第一POLY层中的每一个的顶表面 第一POLY层被暴露以形成接触。

公开(公告)号：US20140374879A1

公开(公告)日：2014-12-25

申请号：US13925940

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

Abstract translation: 由深沟槽电容器引起的晶片弯曲由晶片背面形成的结构改善。 反面的结构包括拉伸膜。 膜可以形成在晶片背面的沟槽内，这增强了它们的作用。 在一些实施例中，晶片用于形成3D-IC器件。 在一些实施例中，3D-IC器件包括高电压或高功率电路。