知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

45 records (took 0.023 seconds)

    Digital time-domain readout circuit method for BioFET sensor cascades
    32.
    发明授权
    Digital time-domain readout circuit method for BioFET sensor cascades 有权

    公开(公告)号：US11243184B2

    公开(公告)日：2022-02-08

    申请号：US16731899

    申请日：2019-12-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Jie Huang ,  Jui-Cheng Huang

    IPC: G01N27/414

    Abstract: Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

    Digital time domain readout circuit for bioFET sensor cascades
    33.
    发明授权
    Digital time domain readout circuit for bioFET sensor cascades 有权

    公开(公告)号：US10533966B2

    公开(公告)日：2020-01-14

    申请号：US15661788

    申请日：2017-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Jie Huang ,  Jui-Cheng Huang

    IPC: G01N27/414

    Abstract: Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

    Digital Time Domain Readout Circuit for BioFET Sensors
    34.
    发明申请
    Digital Time Domain Readout Circuit for BioFET Sensors 审中-公开

    公开(公告)号：US20190033251A1

    公开(公告)日：2019-01-31

    申请号：US15661788

    申请日：2017-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Yu-Jie HUANG ,  Jui-Cheng Huang

    IPC: G01N27/414

    CPC classification number: G01N27/4145 ,  G01N27/4148

    Abstract: Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

    Layout of a MOS array edge with density gradient smoothing
    36.
    发明授权
    Layout of a MOS array edge with density gradient smoothing 有权
    具有密度梯度平滑的MOS阵列边缘的布局

    公开(公告)号：US08759163B2

    公开(公告)日：2014-06-24

    申请号：US13744532

    申请日：2013-01-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Chow Peng ,  Wen-Shen Chou ,  Jui-Cheng Huang

    IPC: H01L21/82 ,  H01L29/00 ,  H01L29/06

    CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/04

    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

    Abstract translation: 公开了一种多步密度梯度平滑布局样式，其中多个单位单元被布置成具有特征密度的阵列。 阵列的一个或多个边缘由第一边缘子阵列界定，该第一边缘子阵列的特征密度小于阵列的特征密度。 第一边缘子阵列由第二边缘子阵列邻接，第二边缘子阵列的特征密度小于第一边缘子阵列的特征密度，并且接近背景电路的特征密度。

    High sensitivity ISFET sensor
    37.
    发明授权
    High sensitivity ISFET sensor 有权

    公开(公告)号：US11293897B2

    公开(公告)日：2022-04-05

    申请号：US16413865

    申请日：2019-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Katherine H. Chiang ,  Jui-Cheng Huang ,  Ke-Wei Su ,  Tung-Tsun Chen ,  Wei Lee ,  Pei-Wen Liu

    IPC: G01N27/414 ,  G01N33/543 ,  G01N27/02

    Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.

    INTEGRATED CELL MONITORING APPARATUS AND METHOD OF USING THE SAME
    38.
    发明申请
    INTEGRATED CELL MONITORING APPARATUS AND METHOD OF USING THE SAME 有权

    公开(公告)号：US20220033759A1

    公开(公告)日：2022-02-03

    申请号：US16944140

    申请日：2020-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsing Hsiao ,  Jui-Cheng Huang

    IPC: C12M1/34 ,  C12M3/00 ,  C12M3/06 ,  C12M1/00 ,  C12N5/00 ,  G01N33/50

    Abstract: Cell monitoring apparatus includes sensing chip and channel module. Sensing chip includes channel region, source and drain regions, and sensing film. The channel region includes first semiconductor material. The source and drain regions are disposed at opposite sides of the channel region, and include a second semiconductor material. Sensing film is disposed on the channel region at a sensing surface of the sensing chip. Channel module is disposed on the sensing surface of sensing chip. A microfluidic channel is formed between the sensing surface of the sensing chip and a proximal surface of the channel module. The microfluidic channel includes a culture chamber and a micro-well. The culture chamber is concave into the proximal surface of the channel module, and overlies the channel region. The micro-well is concave into a side of the culture chamber, and directly faces the sensing film.

Patent Agency Ranking