公开(公告)号：US11631440B2

公开(公告)日：2023-04-18

申请号：US17731248

申请日：2022-04-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/02 ,  G11C7/06

Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.

公开(公告)号：US11605427B2

公开(公告)日：2023-03-14

申请号：US17140605

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Yu-Der Chih ,  Yih Wang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

公开(公告)号：US20220367492A1

公开(公告)日：2022-11-17

申请号：US17876103

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Shao-Yu Chou ,  Yih Wang

IPC: H01L27/112 ,  H01L23/528 ,  H01L23/532 ,  G11C17/16 ,  G06F30/392 ,  H01L23/525 ,  G11C17/18

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

公开(公告)号：US20220366982A1

公开(公告)日：2022-11-17

申请号：US17815076

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Yu-Der Chih ,  Yih Wang

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

公开(公告)号：US20220336037A1

公开(公告)日：2022-10-20

申请号：US17856756

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C29/42 ,  G11C29/20 ,  G11C29/24 ,  G11C29/44

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

公开(公告)号：US20210366915A1

公开(公告)日：2021-11-25

申请号：US17397371

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Chia-En Huang ,  Yen-Huei Chen ,  Yih Wang

IPC: H01L27/11 ,  G11C5/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.

公开(公告)号：US20210249419A1

公开(公告)日：2021-08-12

申请号：US17222740

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Hsun Chiu ,  Yih Wang

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/06 ,  G11C11/412

Abstract: A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

公开(公告)号：US20210098467A1

公开(公告)日：2021-04-01

申请号：US16589806

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Chia-En Huang ,  Yen-Huei Chen ,  Yih Wang

IPC: H01L27/11 ,  G11C5/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.

公开(公告)号：US20250166680A1

公开(公告)日：2025-05-22

申请号：US18511652

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Hsiang Huang ,  Hui Pin Feng ,  Jui-Che Tsai ,  Chia-En Huang ,  Che-Wei Chang ,  Yih Wang

IPC: G11C8/10

Abstract: A semiconductor device includes a plurality of first decoder lines disposed in a first metallization layer and extending in a first direction. Each of the first decoder lines includes at least a first segment and a second segment operatively coupled to a plurality of first memory cells and a plurality of second memory cells, respectively. The first segment and second segment of each of the first decoder lines are arranged side-by-side along the first direction.

公开(公告)号：US12283336B2

公开(公告)日：2025-04-22

申请号：US18439982

申请日：2024-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Philex Ming-Yan Fan ,  Chia-En Huang ,  Yih Wang ,  Jonathan Tsung-Yung Chang

IPC: G11C7/04 ,  G06F1/20 ,  G11C7/22

Abstract: A system includes a high bandwidth memory (HBM) arranged into portions including memory cells, the HBM further including a differentiated dynamic voltage and frequency scaling (DDVFS) device to perform the following: for a first set of one or more of the memory cells in a first one of the portions, the first set including a first one of the memory cells, controlling a temperature of the first set based on one or more first environmental signals corresponding to at least a first transistor in the first memory cell; and for a second set of one or more of the memory cells in a second one of the portions, the second set including a second one of memory cells, controlling a temperature of the second set based on one or more second environmental signals corresponding to at least a second transistor in the second memory cell.