公开(公告)号：US12014131B2

公开(公告)日：2024-06-18

申请号：US18337245

申请日：2023-06-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Hsiung Chen ,  Wen-Hao Chen ,  Hung-Chih Ou ,  Chun-Yao Ku ,  Shao-Huan Wang

IPC: G06F30/30 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F30/398 ,  G06F30/392 ,  G06F115/06 ,  G06F119/06 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G06F30/392 ,  G06F2115/06 ,  G06F2119/06 ,  G06F2119/12

Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

公开(公告)号：US20240096803A1

公开(公告)日：2024-03-21

申请号：US18517706

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Kuo-Nan Yang ,  Jack Liu

IPC: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5286 ,  G06F30/392 ,  G06F30/394 ,  H01L21/76877 ,  H01L23/5226

Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

公开(公告)号：US11855632B2

公开(公告)日：2023-12-26

申请号：US17115571

申请日：2020-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shao-Huan Wang ,  Chun-Chen Chen ,  Sheng-Hsiung Chen ,  Kuo-Nan Yang

IPC: H03K19/17704 ,  H01L23/528 ,  H03K19/17736 ,  H01L27/02 ,  G06F30/392

CPC classification number: H03K19/17704 ,  G06F30/392 ,  H01L23/528 ,  H01L27/0207 ,  H03K19/17736

Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

公开(公告)号：US11854978B2

公开(公告)日：2023-12-26

申请号：US17332072

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Kuo-Nan Yang ,  Jack Liu

IPC: H01L23/528 ,  H01L23/522 ,  G06F30/394 ,  G06F30/392 ,  H01L21/768

CPC classification number: H01L23/5286 ,  G06F30/392 ,  G06F30/394 ,  H01L21/76877 ,  H01L23/5226

Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

公开(公告)号：US11741286B2

公开(公告)日：2023-08-29

申请号：US17365531

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Kai Hsu ,  Sheng-Hsiung Chen ,  Wai-Kei Mak ,  Ting-Chi Wang ,  Yu-Hsiang Cheng ,  Ding-Wei Huang

IPC: G06F30/392 ,  G03F1/70 ,  G06F30/398 ,  G06F111/04 ,  G06F30/31

CPC classification number: G06F30/392 ,  G03F1/70 ,  G06F30/398 ,  G06F30/31 ,  G06F2111/04

Abstract: A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.

公开(公告)号：US11568125B2

公开(公告)日：2023-01-31

申请号：US17212775

申请日：2021-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Ho Che Yu

IPC: G06F30/398 ,  G06F30/392 ,  H01L27/11575

Abstract: A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

公开(公告)号：US11568122B2

公开(公告)日：2023-01-31

申请号：US17376413

申请日：2021-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Po-Hsiang Huang ,  Fong-Yuan Chang ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Sheng-Hsiung Chen ,  Li-Chun Tien ,  Chia-Ming Hsu

IPC: G06F30/3312 ,  G06F30/367 ,  G06F30/398 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  G06F30/392 ,  G06F111/20

Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

公开(公告)号：US20220382958A1

公开(公告)日：2022-12-01

申请号：US17331693

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Huang-Yu Chen ,  Chung-Hsing Wang ,  Jerry Chang Jui Kao

IPC: G06F30/3947

Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

公开(公告)号：US11501052B1

公开(公告)日：2022-11-15

申请号：US17331693

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Huang-Yu Chen ,  Chung-Hsing Wang ,  Jerry Chang Jui Kao

IPC: G06F30/00 ,  G06F30/3947 ,  G06F30/39

Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

公开(公告)号：US10990745B2

公开(公告)日：2021-04-27

申请号：US16559534

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Sheng-Hsiung Chen ,  Shao-Huan Wang ,  Wen-Hao Chen ,  Chun-Yao Ku ,  Hung-Chih Ou

IPC: G06F17/50 ,  G06F30/398 ,  G06F30/3315 ,  G06F30/337 ,  G06F30/396 ,  G03F1/70 ,  G03F1/36 ,  G06F30/394 ,  G06F115/06 ,  G06F119/06 ,  G06F119/12 ,  G06F30/392

Abstract: An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.