公开(公告)号：US5999041A

公开(公告)日：1999-12-07

申请号：US857881

申请日：1997-05-16

申请人： Junichi Nagata ,  Junji Hayakawa ,  Hiroyuki Ban

发明人： Junichi Nagata ,  Junji Hayakawa ,  Hiroyuki Ban

IPC分类号： H03K17/082 ,  H03K17/08

CPC分类号： H03K17/0822

摘要： An output MOS transistor and a current-detecting MOS transistor are connected commonly at their drains and gates. A gate voltage is fed to the gates of these transistors via signal lines. When the voltage of an output terminal is increased in response to excessive load current, a current-mirror circuit consisting of first and second transistors pulls in current from the signal line to reduce the gate voltage. Thus, the output current of output MOS transistor is limited within a predetermined level. Furthermore, a diode, provided in the signal line, produces a voltage drop equivalent to the base-emitter voltage of first transistor. By the function of this diode, the gate-source voltage of output MOS transistor is equalized with the gate-source voltage of current-detecting MOS transistor. As a result, the same operating point can be set for the output transistor and the current-detecting transistor.

摘要翻译： 输出MOS晶体管和电流检测MOS晶体管通常连接在其漏极和栅极。 栅极电压通过信号线馈送到这些晶体管的栅极。 当输出端子的电压响应于过大的负载电流而增加时，由第一和第二晶体管组成的电流镜电路从信号线引出电流以降低栅极电压。 因此，输出MOS晶体管的输出电流被限制在预定的水平。 此外，设置在信号线中的二极管产生等效于第一晶体管的基极 - 发射极电压的电压降。 通过该二极管的功能，输出MOS晶体管的栅极 - 源极电压与电流检测MOS晶体管的栅极 - 源极电压相等。 结果，可以为输出晶体管和电流检测晶体管设置相同的工作点。

公开(公告)号：US5838526A

公开(公告)日：1998-11-17

申请号：US852512

申请日：1997-05-07

申请人： Fukuo Ishikawa ,  Akira Sugiura ,  Masahisa Makino ,  Hiroyuki Ban

发明人： Fukuo Ishikawa ,  Akira Sugiura ,  Masahisa Makino ,  Hiroyuki Ban

IPC分类号： H02H9/04 ,  H02H7/20 ,  H03F1/52 ,  H03K17/00 ,  H03K17/082 ,  H02H9/00

CPC分类号： H03K17/0826 ,  H03K2217/0036

摘要： In a load actuation circuit of an emitter-follower circuit arrangement, a surge detection circuit detects a power surge voltage superposed on a power voltage of a power line. A feed circuit supplies current to a control electrode of an output transistor (i.e. emitter-follower transistor) from the power line to turn on the output transistor forcibly when any power surge voltage is detected by the surge detection circuit. Thus, the power surge voltage is absorbed by the output transistor.

摘要翻译： 在发射极跟随器电路装置的负载驱动电路中，浪涌检测电路检测叠加在电力线的电源电压上的电力浪涌电压。 馈电电路从电源线向输出晶体管（即发射极 - 跟随器晶体管）的控制电极提供电流，以在由浪涌检测电路检测到任何电源浪涌电压时强制导通输出晶体管。 因此，电源浪涌电压被输出晶体管吸收。

公开(公告)号：US5357147A

公开(公告)日：1994-10-18

申请号：US45536

申请日：1993-04-09

申请人： Hiroyuki Ina ,  Takashi Harada ,  Masakazu Honda ,  Hiroyuki Ban ,  Tomohisa Yamamoto

发明人： Hiroyuki Ina ,  Takashi Harada ,  Masakazu Honda ,  Hiroyuki Ban ,  Tomohisa Yamamoto

IPC分类号： H03K5/08 ,  H03K5/19 ,  H03K5/153 ,  H03L7/06

CPC分类号： H03K5/19

摘要： An input signal processing apparatus for use in a comparator which compares an input signal with a reference voltage signal to output a signal inverted in accordance with a comparison result. The apparatus detects the frequency of an input signal from a rotation detecting device such as pickup coil so that a mask time is set in accordance with the detected input signal frequency. The apparatus separates the levels of the input signal and a reference signal to the comparator for the mask time. The mask time is set so as to vary with a first predetermined rate of change when the input signal frequency is below a predetermined frequency and vary with a second predetermined rate of change greater than the first predetermined rate of change when the input signal frequency is above the predetermined frequency. This arrangement can appropriately set the mask time whereby it is possible to prevent the phase shift in waveshaping when the frequency of the input signal is high.

摘要翻译： 一种在比较器中使用的输入信号处理装置，其将输入信号与参考电压信号进行比较，以输出根据比较结果反相的信号。 该装置检测来自诸如拾取线圈的旋转检测装置的输入信号的频率，使得根据检测到的输入信号频率设置掩码时间。 该装置将输入信号和参考信号的电平分离到比较器的屏蔽时间。 掩蔽时间被设定为当输入信号频率低于预定频率时以第一预定变化率变化，并且当输入信号频率高于第一预定变化幅度大于第一预定变化率的第二预定变化率时，屏蔽时间被设置 预定频率。 这种布置可以适当地设置掩模时间，由此当输入信号的频率高时，可以防止波形成形中的相移。

公开(公告)号：US5121347A

公开(公告)日：1992-06-09

申请号：US429937

申请日：1989-11-01

申请人： Tomohisa Yamamoto ,  Hiroyuki Ban ,  Katsuyuki Miyake

发明人： Tomohisa Yamamoto ,  Hiroyuki Ban ,  Katsuyuki Miyake

IPC分类号： G01P3/489 ,  G01R7/00

CPC分类号： G01R7/00 ,  G01P3/489

摘要： An apparatus for driving a gauge having coils in quadrature to generate a resultant magnetic field in accordance with currents applied thereto and having a pointer angularly swept by the field, the apparatus having a memory to store a first data defining a relationship between a first level, indicative of the current applied to one of the coils, and an angle of the pointer. The first level has a continous waveform varying in isoceles trapezoid form over an angle range of 0.degree. to 180.degree.. The first data varies symmetrically with the isoceles trapezoid wave at the 180.degree. pointer angle over an angle range of 180.degree. to 360.degree.. The memory is arranged to store second data defining a relationship between a second level indicative of the current applied to the other coil and the pointer angle. The second level has a continuous waveform phase shifted by 90.degree. from the continuous waveform of the first data. The apparatus also has an output generator to generate output signals indicative of first and second levels related to the first and second data. A driving circuit is responsive to the output signals to drive the coils with currents proportional to the first and second levels. Each continuous waveform of the first and second data is modified so as to be cut triangularly at its corner portions.

摘要翻译： 一种用于驱动具有正交线圈的量规的装置，以根据施加到其上的电流产生合成的磁场，并具有由该场被角度扫描的指针，该装置具有存储器，用于存储限定第一电平之间的关系的第一数据， 指示施加到线圈中的一个的电流以及指针的角度。 第一级在0°至180°的角度范围内具有等间距梯形变化的连续波形。 第一个数据在角度范围为180°至360°的180°指针角度处的等方梯形波对称变化。 存储器被布置为存储定义指示施加到另一个线圈的电流的第二电平与指针角度之间的关系的第二数据。 第二级具有从第一数据的连续波形偏移90°的连续波形相位。 该装置还具有输出发生器，以产生指示与第一和第二数据相关的第一和第二电平的输出信号。 驱动电路响应于输出信号以与第一和第二电平成比例的电流来驱动线圈。 第一和第二数据的每个连续波形被修改为在其角部三角形地切割。

公开(公告)号：US08192703B2

公开(公告)日：2012-06-05

申请号：US12482903

申请日：2009-06-11

申请人： Hiroyuki Ban ,  Koji Noishiki ,  Kazuto Okada ,  Seiichi Yamamoto

发明人： Hiroyuki Ban ,  Koji Noishiki ,  Kazuto Okada ,  Seiichi Yamamoto

IPC分类号： B01J8/00 ,  B01L3/00 ,  B01F5/06

CPC分类号： B01J4/001 ,  B01F5/0471 ,  B01F13/0059 ,  B01J19/249 ,  B01J2219/2453 ,  B01J2219/2458 ,  B01J2219/247 ,  B01J2219/2485 ,  B01J2219/2486 ,  B01J2219/2487 ,  B01J2219/2488 ,  B01J2219/249

摘要： To improve reaction efficiency by increasing a contact area of first and second reactants per unit volume, without reducing dimensions of the inlet paths for the first and second reactants in a layer-thickness direction, a channel includes a first inlet path having the first reactant, a parallel second inlet path separated from the first inlet path and having the second reactant, a junction channel for causing the first and second reactants to join as separate laminar flows, and a parallel reaction channel connected with a downstream side of the junction channel for permitting the laminar flows of the first and second reactants to react at a contact interface thereof. A dimension of the reaction channel in the layer-thickness direction perpendicular to the contact interface is set to be smaller than the sum of the dimensions of the first inlet path and the second inlet path in the layer-thickness direction.

摘要翻译： 为了通过增加每单位体积的第一和第二反应物的接触面积而不减少第一和第二反应物在层厚度方向上的入口路径的尺寸来提高反应效率，通道包括具有第一反应物的第一入口路径， 与第一入口路径分离并具有第二反应物的平行的第二入口路径，用于使第一和第二反应物作为单独层流连接的接合通道，以及与接合通道的下游侧连接的平行反应通道，以允许 第一和第二反应物的层流在其接触界面处反应。 垂直于接触界面的层厚度方向上的反应通道的尺寸被设定为小于层厚度方向上的第一入口通道和第二入口通道的尺寸之和。

公开(公告)号：US20070279272A1

公开(公告)日：2007-12-06

申请号：US11806326

申请日：2007-05-31

申请人： Satoshi Sobue ,  Hiroyuki Ban

发明人： Satoshi Sobue ,  Hiroyuki Ban

IPC分类号： H03M1/78

CPC分类号： H01L27/016 ,  H01L28/20

摘要： A semiconductor device includes a semiconductor substrate, a first wire disposed on the semiconductor substrate, an first insulating layer disposed on the semiconductor substrate and the wire, a first thin film resistor having a first resistance within a predetermined error range, and a second thin film resistor having a second resistance which is allowable to be out of the predetermined error range. A surface of the first insulating layer includes a first area and a second area, in which the second area is located adjacent to the first wire. The first thin film resistor is disposed in the first area, and the second thin film resistor is disposed in the second area.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底上的第一布线，设置在半导体衬底和布线上的第一绝缘层，具有预定误差范围内的第一电阻的第一薄膜电阻和第二薄膜 电阻器具有允许超出预定误差范围的第二电阻。 第一绝缘层的表面包括第一区域和第二区域，其中第二区域位于第一导线附近。 第一薄膜电阻器设置在第一区域中，第二薄膜电阻器设置在第二区域中。

公开(公告)号：US20070217104A1

公开(公告)日：2007-09-20

申请号：US11715421

申请日：2007-03-08

申请人： Shinichiro Nakata ,  Hiroyuki Ban ,  Satoshi Ichikawa

发明人： Shinichiro Nakata ,  Hiroyuki Ban ,  Satoshi Ichikawa

IPC分类号： H02H3/00

CPC分类号： H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： An input protection circuit comprises a reverse flow preventing diode, a series circuit of a diode and a Zener diode, and a current path forming resistor or diode. The reverse flow preventing diode is connected between an input terminal and an internal circuit. The series circuit is connected between the input terminal and a ground. The current path forming resistor or diode is connected between a first common connection point of the reverse flow preventing diode and the internal circuit and a second common connection point of the series circuit, and sets a potential at the first common connection point to be less than a potential at the input terminal when the surge voltage is applied to the input terminal.

摘要翻译： 输入保护电路包括反向阻流二极管，二极管和齐纳二极管的串联电路以及电流路径形成电阻器或二极管。 反向防流二极管连接在输入端和内部电路之间。 串联电路连接在输入端和地之间。 电流通路形成电阻器或二极管连接在反向防流二极管的第一公共连接点和内部电路之间，并且串联电路的第二公共连接点连接，并将第一公共连接点处的电位设置为小于 当浪涌电压施加到输入端时在输入端子处的电位。

公开(公告)号：US20070103139A1

公开(公告)日：2007-05-10

申请号：US11589878

申请日：2006-10-31

申请人： Satoshi Sobue ,  Hiroyuki Ban ,  Shigenori Mori

发明人： Satoshi Sobue ,  Hiroyuki Ban ,  Shigenori Mori

IPC分类号： G05F3/16

CPC分类号： G05F3/265 ,  G05F3/267

摘要： A current mirror circuit includes transistors having bases coupled together and emitters connected to a voltage line. The current mirror circuit further includes a zener diode having an anode connected to the bases and a cathode connected to the voltage line. When a base potential of the transistors decreases, a reverse current of the zener diode increases. Therefore, the zener diode has a resistance and acts as a resistor to clamp the base potential of the transistors. A layout area of the zener diode is much smaller than that of the resistor having a resistance equal to that of the zener diode. The current mirror circuit achieves reduced chip size by using the zener diode instead of the resistor.

摘要翻译： 电流镜电路包括具有耦合在一起的基极和连接到电压线的发射极的晶体管。 电流镜电路还包括具有连接到基极的阳极和连接到电压线的阴极的齐纳二极管。 当晶体管的基极电位降低时，齐纳二极管的反向电流增加。 因此，齐纳二极管具有电阻并且用作钳位晶体管的基极电位的电阻器。 齐纳二极管的布局面积远小于具有等于齐纳二极管电阻的电阻器的布局面积。 电流镜电路通过使用齐纳二极管而不是电阻实现了减小的芯片尺寸。

公开(公告)号：US06922105B2

公开(公告)日：2005-07-26

申请号：US10632849

申请日：2003-08-04

申请人： Hiroshi Imai ,  Mitsuru Aoki ,  Hiroyuki Ban

发明人： Hiroshi Imai ,  Mitsuru Aoki ,  Hiroyuki Ban

IPC分类号： H03F1/52 ,  H03F3/30 ,  H03F3/45 ,  H03F3/26

CPC分类号： H03F3/3071 ,  H03F3/45183 ,  H03F2203/30036 ,  H03F2203/30051 ,  H03F2203/45324 ,  H03F2203/45352 ,  H03F2203/45632 ,  H03F2203/45708

摘要： In an operational amplifier, a differential amplifying circuit is configured to amplify an input voltage inputted from the input terminal. An outputting transistor is connected to the output terminal. A driving transistor is connected to the differential amplifying circuit and the outputting transistor. The driving transistor turns on according to a control signal supplied from the differential amplifying circuit to the driving circuit. The driving transistor is also configured to drive the outputting transistor according to the control signal. A control signal reducing circuit, when a voltage is applied on the driving transistor through the outputting transistor, is configured to reduce the control signal within a range that the driving transistor is kept to on state. The voltage applied on the driving transistor exceeds a predetermined threshold voltage.

摘要翻译： 在运算放大器中，差分放大电路被配置为放大从输入端输入的输入电压。 输出晶体管连接到输出端子。 驱动晶体管连接到差分放大电路和输出晶体管。 驱动晶体管根据从差分放大电路向驱动电路提供的控制信号导通。 驱动晶体管也被配置为根据控制信号来驱动输出晶体管。 当通过输出晶体管对驱动晶体管施加电压时，控制信号降低电路被配置为在驱动晶体管保持导通状态的范围内减少控制信号。 施加在驱动晶体管上的电压超过预定阈值电压。

公开(公告)号：US06646319B2

公开(公告)日：2003-11-11

申请号：US10175306

申请日：2002-06-20

申请人： Hirokazu Itakura ,  Hiroyuki Ban

发明人： Hirokazu Itakura ,  Hiroyuki Ban

IPC分类号： H01L2900

CPC分类号： H01L21/765 ,  H01L21/76264 ,  H01L21/76286 ,  H01L21/76291

摘要： A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.