公开(公告)号：US20240395972A1

公开(公告)日：2024-11-28

申请号：US18794562

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Euijoon Yoon ,  Jehong Oh ,  Jungel Ryu ,  Seungmin Lee ,  Jongmyeong Kim

IPC: H01L33/24 ,  H01L25/075 ,  H01L33/00 ,  H01L33/16 ,  H01L33/32

Abstract: Disclosed are a display device and a manufacturing method thereof. The display device includes a plurality of pixels, a light emitting device provided in each of the plurality of pixels, the light emitting device having a first surface and a second surface, which are opposite to each other, a first electrode electrically connected to the first surface of the light emitting device, a second electrode electrically connected to the second surface of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern is provided to cover a portion of the second surface and to expose a remaining portion of the second surface. The second electrode is electrically connected to the exposed remaining portion of the second surface, and the metal oxide pattern includes single-crystalline or polycrystalline alumina.

公开(公告)号：US12087879B2

公开(公告)日：2024-09-10

申请号：US18303423

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Euijoon Yoon ,  Jehong Oh ,  Jungel Ryu ,  Seungmin Lee ,  Jongmyeong Kim

IPC: H01L33/00 ,  H01L25/075 ,  H01L33/16 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L33/24 ,  H01L25/0753 ,  H01L33/0095 ,  H01L33/16 ,  H01L33/32

Abstract: Disclosed are a display device and a manufacturing method thereof. The display device includes a plurality of pixels, a light emitting device provided in each of the plurality of pixels, the light emitting device having a first surface and a second surface, which are opposite to each other, a first electrode electrically connected to the first surface of the light emitting device, a second electrode electrically connected to the second surface of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern is provided to cover a portion of the second surface and to expose a remaining portion of the second surface. The second electrode is electrically connected to the exposed remaining portion of the second surface, and the metal oxide pattern includes single-crystalline or polycrystalline alumina.

公开(公告)号：US20240266344A1

公开(公告)日：2024-08-08

申请号：US18422924

申请日：2024-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Changbeom Kim ,  Jungho Do ,  Wookyu Kim

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and configured to receive the supply voltage from the power rail, a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail, and a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail.

公开(公告)号：US20240196617A1

公开(公告)日：2024-06-13

申请号：US18511396

申请日：2023-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Lee ,  Jihwan Yu ,  Byungman Ahn ,  Bonghyun Choi

IPC: H10B43/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a substrate comprising a chip region and a scribe lane region including a first key pattern region, a capping insulating layer disposed on the scribe lane region, a barrier metal layer covering the capping insulating layer and an inner wall of a via hole penetrating the capping insulating layer, a substrate layer disposed on the barrier metal layer and filling the via hole, an insulating plate and an upper base layer disposed on the substrate layer, a pattern insulating layer disposed on the capping insulating layer in the first key pattern region, a stacked structure disposed on the upper base layer and the pattern insulating layer, and first pattern structures overlapping the pattern insulating layer in a vertical direction and penetrating the stacked structure and the pattern insulating layer, wherein the pattern insulating layer extends through the barrier metal layer in the first key pattern region.

公开(公告)号：US20240147692A1

公开(公告)日：2024-05-02

申请号：US18496211

申请日：2023-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Lee

IPC: H10B12/00

CPC classification number: H10B12/20 ,  H10B12/01 ,  H10B12/50

Abstract: A semiconductor memory device of the present invention is capable of high performance and high integration, and has an effect of configuring a semiconductor die including a vertical volatile memory structure and a vertical nonvolatile memory structure on one peripheral circuit structure. A semiconductor memory device provided includes a semiconductor substrate, a back gate structure having a cylindrical shape and extending in a vertical direction on the semiconductor substrate and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer, a plurality of semiconductor patterns, each having a ring-shaped horizontal section surrounding the back gate structure, and spaced apart from each other in the vertical direction, and first to third conductive lines surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction.

公开(公告)号：US20230363157A1

公开(公告)日：2023-11-09

申请号：US18352182

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H10B43/40 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：USD800587S1

公开(公告)日：2017-10-24

申请号：US29555244

申请日：2016-02-19

Applicant: Samsung Electronics Co., Ltd.

Designer： Chul-Ho Cho ,  Myeong Su Cheon ,  Sangkyu Kim ,  Seungmin Lee