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    Display substrate and method of manufacturing a display substrate
    31.
    发明授权
    Display substrate and method of manufacturing a display substrate 有权
    显示基板和显示基板的制造方法

    公开(公告)号：US09484362B2

    公开(公告)日：2016-11-01

    申请号：US14262761

    申请日：2014-04-27

    Applicant: Samsung Display Co., LTD.

    Inventor： Dae-Ho Kim ,  Hyun-Jae Na ,  Jae-Neung Kim ,  Yu-Gwang Jeong ,  Myoung-Geun Cha ,  Sang-Gab Kim

    IPC: H01L29/04 ,  H01L27/12 ,  H01L29/417

    CPC classification number: H01L27/1225 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/41733

    Abstract: A display substrate includes an active pattern, a gate electrode, a first insulation layer and a pixel electrode. The active pattern is disposed on a base substrate. The active pattern includes a metal oxide semiconductor. The gate electrode overlaps the active pattern. The first insulation layer covers the gate electrode and the active pattern, and a contact hole is defined in the first insulation layer. The pixel electrode is electrically connected to the active pattern via the contact hole penetrating the first insulation layer. A first angle defined by a bottom surface of the first insulation layer and a sidewall of the first insulation layer exposed by the contact hole is between about 30° and about 50°.

    Abstract translation: 显示基板包括有源图案，栅电极，第一绝缘层和像素电极。 有源图案设置在基底基板上。 有源图案包括金属氧化物半导体。 栅电极与有源图案重叠。 第一绝缘层覆盖栅电极和有源图案，并且在第一绝缘层中限定接触孔。 像素电极经由穿过第一绝缘层的接触孔电连接到有源图案。 由第一绝缘层的底表面和由接触孔露出的第一绝缘层的侧壁限定的第一角度在约30°至约50°之间。

    METHOD OF FORMING A FINE PATTERN
    32.
    发明申请
    METHOD OF FORMING A FINE PATTERN 有权
    形成精细图案的方法

    公开(公告)号：US20160138169A1

    公开(公告)日：2016-05-19

    申请号：US14718127

    申请日：2015-05-21

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jung-Ha SON ,  Su-Bin Bae ,  Yu-Gwang Jeong ,  Lei Xie ,  Yun-Jong Yeo ,  Joo-Hyung Lee

    IPC: C23F1/02

    CPC classification number: G03F7/0002 ,  C23F1/02 ,  G02F1/133536 ,  G02F2001/133548 ,  G02F2202/36 ,  H01L21/0337 ,  H01L21/32139

    Abstract: A method of forming a fine pattern includes providing a first metal layer on a base substrate, providing a first passivation layer on the first metal layer, providing a mask pattern on the first passivation layer, providing a partitioning wall pattern having a reverse taper shape by etching the first passivation layer, coating a composition having a block copolymer between the partitioning wall patterns adjacent each other, providing a self-aligned pattern by heating the composition, and providing a metal pattern by etching the first metal layer using the self-aligned pattern as a mask.

    Abstract translation: 形成精细图案的方法包括在基底基板上提供第一金属层，在第一金属层上提供第一钝化层，在第一钝化层上提供掩模图案，通过以下步骤提供具有倒锥形的分隔壁图案： 蚀刻第一钝化层，在彼此相邻的分隔壁图案之间涂覆具有嵌段共聚物的组合物，通过加热组合物提供自对准图案，以及通过使用自对准图案蚀刻第一金属层来提供金属图案 作为面具。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    33.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20140117361A1

    公开(公告)日：2014-05-01

    申请号：US13830269

    申请日：2013-03-14

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

    Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

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