GAIN STAGE DEGENERATION INDUCTOR SWITCHING WITHOUT THE USE OF SWITCHES

    公开(公告)号:US20220255519A1

    公开(公告)日:2022-08-11

    申请号:US17566324

    申请日:2021-12-30

    Abstract: Disclosed herein are signal amplifier architectures that provide a plurality of gain modes. Different gain modes can use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture can be configured to also provide targeted impedance in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture, improving the noise figure (NF), improving impedance matching, and eliminating the need for control logic associated with the degeneration block or matrix.

    Switching circuits for wireless applications

    公开(公告)号:US10056935B2

    公开(公告)日:2018-08-21

    申请号:US15497120

    申请日:2017-04-25

    Inventor: Junhyung Lee

    Abstract: Switching circuits for wireless applications. In some embodiments, a switching circuit can include a common node and a plurality of series arm switches with each being capable of connecting the common node and a respective signal node. The switching circuit can further include a shunt arm switch for each of the series arm switches. The shunt arm switch can be capable of connecting the signal node of the respective series arm switch to a ground. The switching circuit can further include a compensation circuit coupled to the common node and configured to compensate for a parasitic effect resulting from some or all of the series arm switches and the shunt arm switches.

    Bypass path loss reduction
    40.
    发明授权

    公开(公告)号:US09847804B2

    公开(公告)日:2017-12-19

    申请号:US14678390

    申请日:2015-04-03

    CPC classification number: H04B1/18 H04B1/44 H04B7/04

    Abstract: Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.

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