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公开(公告)号：US11183984B2
公开(公告)日：2021-11-23
申请号：US16680304
申请日：2019-11-11
Applicant: SKYWORKS SOLUTIONS, INC.
IPC: H03F3/72 , H03F3/68 , H03F1/22 , H03G3/30 , H03F1/32 , H03F1/56 , H03G1/00 , H03G3/00 , H03F3/195 , H03F3/213
Abstract: Variable-phase amplifier circuits and devices. In some embodiments, an amplifier can include a variable-gain stage having a plurality of switchable amplification branches, with each being capable of being activated, such that a combination of one or more activated amplification branches provides respective gain level and phase shift. The plurality of switchable amplification branches can be configured such that the phase shift provided by each combination of one or more activated amplification branches compensates for a phase shift associated with the amplifier operating with the respective gain level of the variable-gain stage.
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公开(公告)号：US20210143859A1
公开(公告)日：2021-05-13
申请号：US17069745
申请日：2020-10-13
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
Abstract: Described herein are methods for amplifying radio-frequency signals using a variable-gain amplifier with a plurality of input nodes. The methods provide a plurality of gain modes with a low gain mode or bypass mode that follows a bypass path through the variable-gain amplifier and a plurality of higher gain modes that take advantage of tailored impedances for particular gain modes. The tailored impedances can be configured to improve linearity of the amplification process in targeted gain modes. The methods can selectively couple the bypass path to a reference potential node in the plurality of higher gain modes and can selectively decouple the input nodes from a degeneration switching block in the bypass mode.
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公开(公告)号：US10804951B2
公开(公告)日：2020-10-13
申请号：US16736777
申请日：2020-01-07
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
Abstract: Described herein are variable-gain amplifier configurations that include a multi-input gain stage, a cascode buffer, and a bypass block. Degeneration switching blocks can be used for the entire multi-input gain stage or for individual input nodes of the multi-input gain stage. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.
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公开(公告)号：US10778150B2
公开(公告)日：2020-09-15
申请号：US16546261
申请日：2019-08-20
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
IPC: H03F3/72 , H03F1/02 , H03F3/19 , H03F1/56 , H03G3/30 , H03F1/22 , H03F1/32 , H03F3/193 , H03G1/00 , H03G5/28 , H04B1/3827
Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers have a first active core with amplification chains for each of a plurality of inputs and a second active core with a single amplification chain to amplify signals received at the plurality of inputs.
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公开(公告)号：US20180062600A1
公开(公告)日：2018-03-01
申请号：US15690762
申请日：2017-08-30
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung LEE , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
CPC classification number: H03G3/3042 , H03F1/223 , H03F1/56 , H03F3/193 , H03F2200/211 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/3063 , H03G2201/106 , H04B7/08 , H04B7/0842
Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths that allow signals in a high gain mode to bypass attenuation. This advantageously reduces or eliminates performance penalties in the high gain mode. The programmable attenuators can be configured to improve linearity of the amplification process through pre-LNA attenuation in targeted gain modes. In addition, described herein are variable gain amplifiers with embedded attenuators in a switching network. The attenuators can be embedded onto switches and can be configured to have little or no effect on a noise factor in a high gain mode because the switching network can provide an attenuation bypass in a high gain mode and an attenuation in other gain modes. The programmable attenuators can be embedded onto a multi-input LNA architecture.
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Patent Agency Ranking
6.发明授权Apparatus and methods for digital step attenuators with small output glitch 有权具有小输出毛刺的数字步进衰减器的装置和方法公开(公告)号：US09473109B2
公开(公告)日：2016-10-18
申请号：US14704199
申请日：2015-05-05
Applicant: Skyworks Solutions, Inc.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC classification number: H03H11/245 , H03H11/24 , H04M1/0277
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.
Abstract translation: 本文提供了用于数字步进衰减器的装置和方法。 在某些配置中，DSA包括可以使用多个开关电路在衰减模式或旁路模式中设置的多个DSA级。 多个开关电路的第一开关电路包括场效应晶体管（FET）开关，栅极电阻，一个或多个栅极电阻旁路开关和脉冲发生电路。 栅极电阻器电连接在开关控制输入端和FET开关的栅极之间，开关控制信号可以提供给开关控制输入端以接通或关断FET开关。 响应于检测开关控制信号的上升沿和/或下降沿，脉冲发生电路可以控制一个或多个栅极电阻旁路开关绕过栅极电阻。
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公开(公告)号：US12021495B2
公开(公告)日：2024-06-25
申请号：US17566334
申请日：2021-12-30
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Yan Yan , Bumkyum Kim , Aravind Kumar Padyana , Joshua Haeseok Cho , Rimal Deep Singh , Bipul Agarwal
CPC classification number: H03G3/3036 , H03F3/19 , H04B1/40 , H03F2200/451 , H03G2201/103 , H03G2201/307
Abstract: Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.
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公开(公告)号：US11563460B2
公开(公告)日：2023-01-24
申请号：US17069745
申请日：2020-10-13
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
Abstract: Described herein are methods for amplifying radio-frequency signals using a variable-gain amplifier with a plurality of input nodes. The methods provide a plurality of gain modes with a low gain mode or bypass mode that follows a bypass path through the variable-gain amplifier and a plurality of higher gain modes that take advantage of tailored impedances for particular gain modes. The tailored impedances can be configured to improve linearity of the amplification process in targeted gain modes. The methods can selectively couple the bypass path to a reference potential node in the plurality of higher gain modes and can selectively decouple the input nodes from a degeneration switching block in the bypass mode.
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公开(公告)号：US20220255520A1
公开(公告)日：2022-08-11
申请号：US17566334
申请日：2021-12-30
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Yan Yan , Bumkyum Kim , Aravind Kumar Padyana , Joshua Haeseok Cho , Rimal Deep Singh , Bipul Agarwal
Abstract: Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.
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公开(公告)号：US20200052652A1
公开(公告)日：2020-02-13
申请号：US16546261
申请日：2019-08-20
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
IPC: H03F1/02 , H03F3/19 , H03F1/56 , H03G3/30 , H03F1/22 , H03F1/32 , H03F3/193 , H03F3/72 , H03G1/00 , H03G5/28
Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers have a first active core with amplification chains for each of a plurality of inputs and a second active core with a single amplification chain to amplify signals received at the plurality of inputs.
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