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    THREE-DIMENSIONAL VERTICAL CO-SPIRAL INDUCTORS
    31.
    发明公开
    THREE-DIMENSIONAL VERTICAL CO-SPIRAL INDUCTORS 审中-公开

    公开(公告)号：US20240021353A1

    公开(公告)日：2024-01-18

    申请号：US17812772

    申请日：2022-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Kai LIU ,  Ranadeep DUTTA

    IPC: H01F17/00 ,  H01F27/28

    CPC classification number: H01F17/0013 ,  H01F27/2804 ,  H01F2027/2809

    Abstract: One or more aspects include apparatuses, systems including co-spiral inductors and methods for fabricating the same. In at least one aspect, a co-spiral inductor includes a plurality of turns, each of the plurality of turns being displaced both vertically and horizontally from a next successive turn. The plurality of turns is formed from traces on different metal layers formed on a substrate. The co-spiral inductor includes a plurality of insulators configured to electrically insulate each of the plurality of turns. The co-spiral inductor includes a plurality of interconnects configured to couple each of the plurality of turns to at least one other turn.

    CAPACITOR EMBEDDED 3D RESONATOR FOR BROADBAND FILTER
    32.
    发明公开
    CAPACITOR EMBEDDED 3D RESONATOR FOR BROADBAND FILTER 审中-公开

    公开(公告)号：US20230275004A1

    公开(公告)日：2023-08-31

    申请号：US17682868

    申请日：2022-02-28

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Kai LIU ,  Ranadeep DUTTA

    IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H03H7/01

    CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L21/76898 ,  H03H7/0115 ,  H01L23/5227

    Abstract: An integrated circuit (IC) includes a substrate and a first through substrate via (TSV) in the substrate. The first TSV includes a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate composed of a first metallization layer on an inner surface of the first TSV. The first MIM capacitor includes a MIM insulator layer on the first plate. The first MIM capacitor includes a second plate composed of a second metallization layer on the MIM insulator layer. The IC includes a 3D inductor. The 3D inductor includes a second TSV in the substrate. The 3D inductor includes a first trace on a first surface of the substrate, coupled to a first end of the second TSV. The 3D inductor further includes a second trace on a second surface of the substrate and coupled to a second end of the second TSV and a second end of the first TSV.

    HIGH DENSITY SILICON BASED CAPACITOR
    33.
    发明申请
    HIGH DENSITY SILICON BASED CAPACITOR 有权

    公开(公告)号：US20230092429A1

    公开(公告)日：2023-03-23

    申请号：US17483403

    申请日：2021-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

    IPC: H01L29/94 ,  H01L49/02 ,  H01L29/66 ,  H01L21/768 ,  H01L23/48

    Abstract: Disclosed are devices having a metal-insulator-metal (MIM) capacitor and methods for fabricating the devices. The MIM capacitor includes a plurality of trenches in a Silicon (Si) substrate; a porous Si surface formed in the plurality of trenches, where the porous Si surface has an irregular surface on sidewalls and bottoms of the plurality of trenches; an oxide layer conformally disposed on the porous Si surface; a first plate conformally disposed on the oxide layer; a first dielectric layer conformally disposed on the first plate; and a second plate conformally disposed on the first dielectric, where the first plate, the first dielectric layer, and the second plate, each have an irregular surface that generally conforms to the irregular surface of the porous Si surface.

    THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH PASSIVE ELEMENTS FORMED BY HYBRID BONDING
    36.
    发明申请
    THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH PASSIVE ELEMENTS FORMED BY HYBRID BONDING 有权

    公开(公告)号：US20210398957A1

    公开(公告)日：2021-12-23

    申请号：US16906509

    申请日：2020-06-19

    Applicant: QUALCOMM Incorporated

    Inventor： Je-Hsiung LAN ,  Ranadeep DUTTA ,  Jonghae KIM

    IPC: H01L25/16 ,  H01L23/00 ,  H01L49/02 ,  H01L27/092 ,  H03H9/17

    Abstract: A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.

    DIE-TO-WAFER HYBRID BONDING WITH FORMING GLASS
    37.
    发明申请
    DIE-TO-WAFER HYBRID BONDING WITH FORMING GLASS 有权

    公开(公告)号：US20210143071A1

    公开(公告)日：2021-05-13

    申请号：US16682554

    申请日：2019-11-13

    Applicant: QUALCOMM Incorporated

    Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

    IPC: H01L23/15 ,  H01L21/02 ,  H01L21/8238

    Abstract: Certain aspects provide a three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. For example, certain aspects provide a semiconductor device that generally includes one or more first integrated circuits (ICs), a first plurality of pads coupled to components of the one or more first ICs, one or more second ICs, forming glass (FG) material disposed adjacent to the one or more second ICs, and a second plurality of pads, wherein at least one of the second plurality of pads is coupled to components of the one or more second ICs, and wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads.

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