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    PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR
    31.
    发明申请
    PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR 审中-公开
    多线程处理器中的并联指令的并行分配

    公开(公告)号：US20140258680A1

    公开(公告)日：2014-09-11

    申请号：US13785017

    申请日：2013-03-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti ,  Jose Fridman

    IPC: G06F9/38

    CPC classification number: G06F9/3881 ,  G06F9/3802

    Abstract: Techniques are addressed for parallel dispatch of coprocessor and thread instructions to a coprocessor coupled to a threaded processor. A first packet of threaded processor instructions is accessed from an instruction fetch queue (IFQ) and a second packet of coprocessor instructions is accessed from the IFQ. The IFQ includes a plurality of thread queues that are each configured to store instructions associated with a specific thread of instructions. A dispatch circuit is configured to select the first packet of thread instructions from the IFQ and the second packet of coprocessor instructions from the IFQ and send the first packet to a threaded processor and the second packet to the coprocessor in parallel. A data port is configured to share data between the coprocessor and a register file in the threaded processor. Data port operations are accomplished without affecting operations on any thread executing on the threaded processor.

    Abstract translation: 解决了将协处理器和线程指令并行调度到耦合到线程处理器的协处理器的技术。 从指令队列（IFQ）访问第一个线程处理器指令包，并从IFQ访问第二个协处理器指令包。 IFQ包括多个线程队列，每个线程队列被配置为存储与特定指令线程相关联的指令。 调度电路被配置为从IFQ和来自IFQ的协处理器指令的第二分组选择线程指令的第一分组，并且将第一分组并行地发送到线程处理器，并将第二分组发送到协处理器。 数据端口被配置为在协处理器和线程处理器中的寄存器文件之间共享数据。 完成数据端口操作，而不影响在线程处理器上执行的任何线程的操作。

    INSTRUCTION CACHE HAVING A MULTI-BIT WAY PREDICTION MASK
    33.
    发明申请
    INSTRUCTION CACHE HAVING A MULTI-BIT WAY PREDICTION MASK 有权
    具有多点预测掩码的指令缓存

    公开(公告)号：US20140181405A1

    公开(公告)日：2014-06-26

    申请号：US13721317

    申请日：2012-12-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

    IPC: G06F12/08

    CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3832 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.

    Abstract translation: 在特定实施例中，一种装置包括配置成基于预测掩模值有选择地设置多位方式预测掩模的比特的控制逻辑。 控制逻辑与包括数据阵列的指令高速缓存相关联。 数据阵列的线路驱动器的一个子集是响应于多位方式预测掩码启用的。 线路驱动器的子集包括多个线路驱动器。

    Cache Memory with Write Through, No Allocate Mode
    34.
    发明申请
    Cache Memory with Write Through, No Allocate Mode 有权
    高速缓存内存写入，无分配模式

    公开(公告)号：US20130346705A1

    公开(公告)日：2013-12-26

    申请号：US13655593

    申请日：2012-10-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Manojkumar Pyla ,  Lucian Codrescu

    IPC: G06F12/08

    CPC classification number: G06F12/0804 ,  G06F12/0888 ,  G06F2212/601

    Abstract: In a particular embodiment, a method of managing a cache memory includes, responsive to a cache size change command, changing a mode of operation of the cache memory to a write through/no allocate mode. The method also includes processing instructions associated with the cache memory while executing a cache clean operation when the mode of operation of the cache memory is the write through/no allocate mode. The method further includes after completion of the cache clean operation, changing a size of the cache memory and changing the mode of operation of the cache to a mode other than the write through/no allocate mode.

    Abstract translation: 在特定实施例中，管理高速缓冲存储器的方法响应于高速缓存大小改变命令，将高速缓冲存储器的操作模式改变为写/无分配模式。 当高速缓冲存储器的操作模式是写/无分配模式时，该方法还包括处理与高速缓存存储器相关联的指令，同时执行高速缓存清理操作。 该方法还包括在完成高速缓存清理操作之后，改变高速缓冲存储器的大小并将高速缓存的操作模式改变为除了写/无分配模式以外的模式。

    USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES
    35.
    发明申请
    USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES 审中-公开
    使用呼叫功能地址的最小重要位置切换处理器模式

    公开(公告)号：US20130205115A1

    公开(公告)日：2013-08-08

    申请号：US13655499

    申请日：2012-10-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Charles Joseph Tabony ,  Erich James Plondke ,  Lucian Codrescu ,  Suresh K. Venkumahanti ,  Evandro Carlos Menezes

    IPC: G06F9/30 ,  G06F9/315

    CPC classification number: G06F9/30189 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/322 ,  G06F9/3816

    Abstract: Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

    Abstract translation: 在处理系统中跟踪和切换执行模式的系统和方法。 处理系统被配置为在至少两个指令执行三极管中执行指令，包括从经典/对准模式和压缩/未对准模式选择的第一和第二执行模式。 所选择的指令（例如呼叫和返回）的目标地址在压缩模式下被强制地未对准，诸如压缩模式中的目标地址的最低有效位（对齐比特）之类的一个或多个比特与对应的比对比特不同 在经典模式下。 当在第一模式中执行期间遇到所选择的指令时，将操作切换到第二模式的决定是基于分析所选指令的目标地址的对准比特。

    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS
    38.
    发明申请
    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS 有权
    多重执行机构的系统与方法

    公开(公告)号：US20140282508A1

    公开(公告)日：2014-09-18

    申请号：US13829023

    申请日：2013-03-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： Erich James Plondke ,  Lucian Codrescu ,  Christopher Edward Koob ,  Piyush Patel ,  Thomas Andrew Sartorius

    IPC: G06F9/455

    CPC classification number: G06F9/45533 ,  G06F9/5016 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/151 ,  G06F2212/656

    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

    Abstract translation: 一种装置包括可在第一组处理器上执行的主管理程序，以及可在第二组处理器上执行的辅管理程序。 主管理程序可以定义资源的设置，次管理程序可以使用基于主管理程序定义的设置的资源。 例如，主管理程序可以为二级管理程序编程内存地址转换映射。 主管理程序和辅助管理程序可以包括它们自己的调度器。

    VECTOR REGISTER ADDRESSING AND FUNCTIONS BASED ON A SCALAR REGISTER DATA VALUE
    40.
    发明申请
    VECTOR REGISTER ADDRESSING AND FUNCTIONS BASED ON A SCALAR REGISTER DATA VALUE 有权
    基于标量寄存器数据值的矢量寄存器寻址和功能

    公开(公告)号：US20140244967A1

    公开(公告)日：2014-08-28

    申请号：US13777297

    申请日：2013-02-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ajay A. Ingle ,  Marc M. Hoffman ,  Jose Fridman ,  Lucian Codrescu

    IPC: G06F9/30

    CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

    Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified, in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

    Abstract translation: 提供了用于执行向量对齐指令的技术。 第一处理器中的标量寄存器文件被配置为与向第二处理器共享一个或多个寄存器值，所述寄存器值是根据在矢量对准指令中指定的Rt地址从标量寄存器文件访问的一个或多个寄存器值，其中开始 从共享寄存器值之一确定位置。 第二处理器中的对准电路被配置为根据向量对准指令将矢量寄存器文件（VRF）的起始Vu寄存器内的起始位置与VRF的最后一个Vu寄存器的结束位置之间标识的数据进行对准。 存储电路被配置为从对准电路中选择对准的数据，并根据由向量对准指令指定的对准存储地址将对准的数据存储在向量寄存器文件中。

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