公开(公告)号：US20170062388A1

公开(公告)日：2017-03-02

申请号：US15347803

申请日：2016-11-10

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Yu-Hua Huang ,  Wei-Che Huang ,  Ming-Tzong Yang

IPC: H01L25/065 ,  H01L23/00

Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.

Abstract translation: 一种封装结构，包括：衬底，其具有设置在所述衬底的第一表面处的至少一个导电单元; 至少一个第一管芯，设置在所述衬底的第二表面上; 连接层，设置在第一管芯上; 设置在所述连接层上的第二模具，其中所述连接层包括用于连接所述第一模具的至少一个凸块; 和至少一个接合线。 连接层具有第一触摸侧和第二触摸侧，第一触摸面接触第一模具的第一表面，第二触摸面接触第二模具的第二表面，第一触摸侧的区域小于 对于第一管芯的第一表面和第一管芯的尺寸等于第二管芯的尺寸。

公开(公告)号：US09543232B2

公开(公告)日：2017-01-10

申请号：US14601440

申请日：2015-01-21

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L29/06 ,  H01L21/761 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.

Abstract translation: 提供一种半导体封装结构及其形成方法。 半导体封装结构包括衬底，并且衬底具有正面和背面。 半导体封装结构包括在衬底中形成的穿硅通孔（TSV）互连结构; 以及形成在所述衬底中的第一保护环掺杂区域和第二保护环掺杂区域，并且所述第一保护环掺杂区域和所述第二保护环掺杂区域与所述TSV互连结构相邻。

公开(公告)号：US09425098B2

公开(公告)日：2016-08-23

申请号：US14621703

申请日：2015-02-13

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/268 ,  H01L21/306 ,  H01L23/522 ,  H01L31/18 ,  H01L23/48 ,  H01L21/02 ,  H01L23/66

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate has a first thickness, an electronic component disposed on the front side of the semiconductor substrate, and an interconnect structure disposed on the electronic component. The method further performs a thinning process to remove a portion of the semiconductor substrate from the back side thereof. The method then removes a portion of the thinned semiconductor substrate and a portion of a dielectric layer of the interconnect structure from a back side of the thinned semiconductor substrate until a first metal layer pattern of the interconnect structure is exposed, thereby forming a through hole. Finally, the method forms a TSV structure in the through hole, and mounts the electronic device chip on a base.

Abstract translation: 一种制造电子器件封装的方法，提供了一种电子器件芯片，其中电子器件芯片包括具有正面和背面的半导体衬底，其中半导体衬底具有第一厚度，电子部件设置在第一厚度的前侧 半导体衬底和布置在电子部件上的互连结构。 该方法还进行薄膜化处理以从其背面去除半导体衬底的一部分。 然后，该方法从减薄的半导体衬底的背面去除一部分减薄的半导体衬底和互连结构的电介质层的一部分，直到互连结构的第一金属层图案被暴露，从而形成通孔。 最后，该方法在通孔中形成TSV结构，并将电子设备芯片安装在基座上。

公开(公告)号：US09269664B2

公开(公告)日：2016-02-23

申请号：US13846138

申请日：2013-03-18

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Yu-Hua Huang ,  Wei-Che Huang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect and a method for fabricating the same. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate. A through hole is formed through the semiconductor substrate. A TSV interconnect is disposed in a through hole. A conductive layer lines a sidewall of the through hole, surrounding the TSV interconnect.

Abstract translation: 本发明提供一种具有贯通硅通孔（TSV）互连的半导体封装及其制造方法。 具有TSV互连的半导体封装的示例性实施例包括半导体衬底。 通过半导体衬底形成通孔。 TSV互连设置在通孔中。 导电层将通孔的侧壁连接起来，围绕TSV互连。

公开(公告)号：US09257392B2

公开(公告)日：2016-02-09

申请号：US13855873

申请日：2013-04-03

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Yu-Hua Huang ,  Wei-Che Huang

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/11 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42356 ,  H01L2224/02372 ,  H01L2224/0912 ,  H01L2225/06541

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.

Abstract translation: 本发明提供一种具有通硅通孔（TSV）互连的半导体封装。 具有TSV互连的半导体封装的示例性实施例包括具有前侧和后侧的半导体衬底。 接触阵列设置在半导体衬底的前侧。 隔离结构设置在半导体衬底中，位于接触阵列的下面。 TSV互连通过半导体衬底形成，与接触阵列和隔离结构重叠。

公开(公告)号：US20150364549A1

公开(公告)日：2015-12-17

申请号：US14301348

申请日：2014-06-11

Applicant: MEDIATEK INC.

Inventor： Tung-Hsing Lee ,  Ming-Tzong Yang ,  Wei-Che Huang ,  Cheng-Chou Hung

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/0653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiC device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiC.

Abstract translation: 具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 在所述内部区域中的所述半导体衬底上的SiC器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。 至少一个虚拟图案包含SiC。

公开(公告)号：US09190976B2

公开(公告)日：2015-11-17

申请号：US13804206

申请日：2013-03-14

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang

IPC: H03H7/01 ,  H03H3/00 ,  H01P1/203 ,  H01P7/08

CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.

Abstract translation: 本发明的实施例提供一种无源器件单元。 无源器件单元具有衬底层，无源器件以及形成在衬底层和无源器件之间的中间层。 中间层包括多个LC谐振器。

公开(公告)号：US20130265121A1

公开(公告)日：2013-10-10

申请号：US13804206

申请日：2013-03-14

Applicant: MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang

IPC: H03H7/01 ,  H03H3/00

CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.

Abstract translation: 本发明的实施例提供一种无源器件单元。 无源器件单元具有衬底层，无源器件和形成在衬底层和无源器件之间的中间层。 中间层包括多个LC谐振器。