公开(公告)号：US11222862B2

公开(公告)日：2022-01-11

申请号：US16658675

申请日：2019-10-21

Applicant: International Business Machines Corporation

Inventor： Qianwen Chen ,  Bing Dang ,  Russell Budd ,  Bo Wen ,  Li-Wen Hung ,  Jae-Woong Nah ,  John Knickerbocker

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/00

Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.

公开(公告)号：US20210366789A1

公开(公告)日：2021-11-25

申请号：US16882624

申请日：2020-05-25

Applicant: International Business Machines Corporation

Inventor： John Knickerbocker ,  Bing Dang ,  Qianwen Chen ,  Joshua M. Rubin ,  Arvind Kumar

IPC: H01L21/66 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

公开(公告)号：US10687425B2

公开(公告)日：2020-06-16

申请号：US15821446

申请日：2017-11-22

Applicant: International Business Machines Corporation

Inventor： Paul S. Andry ,  Qianwen Chen ,  Bing Dang ,  John U. Knickerbocker ,  Minhua Lu ,  Robert J. Polastre ,  Bucknell C. Webb

IPC: H05K3/30 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K1/11 ,  H05K1/03 ,  H05K1/02 ,  G01R31/44 ,  G01R31/309 ,  G01R31/28 ,  H05K13/00

Abstract: An electro-optical module assembly is provided that includes a flexible substrate having a first surface and a second surface opposite the first surface, wherein the flexible substrate contains an opening located therein that extends from the first surface to the second surface. An optical component is located on the second surface of the flexible substrate and is positioned to have a surface exposed by the opening. At least one electronic component is located on a first portion of the first surface of the flexible substrate, and at least one micro-energy source is located on a second portion of the first surface of the flexible substrate.

公开(公告)号：US20200146576A1

公开(公告)日：2020-05-14

申请号：US16738040

申请日：2020-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Huan Hu ,  Zheng Xu ,  Xin Zhang

IPC: A61B5/0408 ,  A61B5/00 ,  A61B5/0492 ,  A61B5/0496 ,  A61B5/0478 ,  B82Y40/00

Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.

公开(公告)号：US10535994B2

公开(公告)日：2020-01-14

申请号：US15804605

申请日：2017-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Yang Liu ,  Dongbing Shao ,  Zheng Xu

IPC: H02H9/04 ,  H05F3/00 ,  H05K9/00 ,  H05F3/04 ,  H05K1/02 ,  H01T4/10

Abstract: An air gap metal tip structure is provided for ESD protection that includes a lower substrate and an upper substrate disposed above the lower substrate. The air gap metal tip structure includes a first and a second metal tip disposed along at least one horizontal axis that is parallel to the upper substrate and the lower substrate. The air gap metal tip structure includes an air chamber formed between the upper and lower substrates within which the first and second metal tips are disposed. The air chamber includes a portion between points of the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an occurrence of an arc between the tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the tips to maintain the ESD protection for subsequent arcs.

公开(公告)号：US20190311082A1

公开(公告)日：2019-10-10

申请号：US16433675

申请日：2019-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Li-Wen Hung ,  Wanki Kim ,  John U. Knickerbocker ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC: G06F17/50 ,  H01L25/07 ,  G06F15/78 ,  H01L25/11 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

公开(公告)号：US10393798B2

公开(公告)日：2019-08-27

申请号：US15821403

申请日：2017-11-22

Applicant: International Business Machines Corporation

Inventor： Paul S. Andry ,  Qianwen Chen ,  Bing Dang ,  John U. Knickerbocker ,  Minhua Lu ,  Robert J. Polastre ,  Bucknell C. Webb

IPC: G01R31/309 ,  G01R31/28 ,  H05K3/34 ,  H05K3/30 ,  H05K3/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K1/02 ,  H05K13/00

Abstract: An electro-optical module assembly is provided that includes a flexible substrate having a first surface and a second surface opposite the first surface, wherein the flexible substrate contains an opening located therein that extends from the first surface to the second surface. An optical component is located on the second surface of the flexible substrate and is positioned to have a surface exposed by the opening. At least one electronic component is located on a first portion of the first surface of the flexible substrate, and at least one micro-energy source is located on a second portion of the first surface of the flexible substrate.

公开(公告)号：US20190088481A1

公开(公告)日：2019-03-21

申请号：US15859608

申请日：2017-12-31

Applicant: International Business Machines Corporation

Inventor： Russell A. Budd ,  Qianwen Chen ,  Bing Dang ,  Jeffrey D. Gelorme ,  Li-wen Hung ,  John U. Knickerbocker

IPC: H01L21/20 ,  H01L21/683 ,  B24B7/22

CPC classification number: H01L21/2007 ,  B24B7/228 ,  H01L21/6835 ,  H01L23/49827 ,  H01L2221/68318 ,  H01L2221/6834

Abstract: Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

公开(公告)号：US20180323472A1

公开(公告)日：2018-11-08

申请号：US15585924

申请日：2017-05-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Bing Dang ,  John U. Knickerbocker

IPC: H01M10/0585 ,  H01M10/0525 ,  A61B5/00

CPC classification number: H01M10/0585 ,  A61B5/681 ,  A61B5/6861 ,  A61B2560/0214 ,  H01M10/0525 ,  H01M2220/30

Abstract: A method for integrating a thin film microbattery with electronic circuitry includes forming a release layer over a handler, forming a thin film microbattery over the release layer of the handler, removing the thin film microbattery from the handler, depositing the thin film microbattery on an interposer, forming electronic circuitry on the interposer, and sealing the thin film microbattery and the electronic circuitry to create individual microbattery modules.

公开(公告)号：US20180113969A1

公开(公告)日：2018-04-26

申请号：US15626582

申请日：2017-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Li-Wen Hung ,  Wanki Kim ,  John U. Knickerbocker ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC: G06F17/50 ,  G06F15/78

CPC classification number: G06F17/5027 ,  G06F15/7803 ,  G06F15/7807 ,  G06F15/7857 ,  G06F15/803 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/17 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L25/115 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80006 ,  H01L2224/81005 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.