公开(公告)号：US09735237B2

公开(公告)日：2017-08-15

申请号：US14752446

申请日：2015-06-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/872 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L29/0634 ,  H01L29/6606 ,  H01L29/8083 ,  H01L29/872

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.

公开(公告)号：US20150236151A1

公开(公告)日：2015-08-20

申请号：US14182765

申请日：2014-02-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： James Jay McMahon ,  Ljubisa Dragoljub Stevanovic ,  Stephen Daley Arthur ,  Thomas Bert Gorczyca ,  Richard Alfred Beaupre ,  Zachary Matthew Stum ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/16

CPC classification number: H01L29/7827 ,  H01L21/045 ,  H01L21/049 ,  H01L21/28247 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7816

Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.

Abstract translation: 介绍了半导体器件。 该器件包括具有碳化硅的半导体层，并具有第一表面和第二表面。 栅极绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅极绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的角部处的氧化物，因此栅极绝缘层在角部具有比层的中心处的厚度更大的厚度。 还提供了一种用于制造该装置的方法。

公开(公告)号：US20150115284A1

公开(公告)日：2015-04-30

申请号：US14396852

申请日：2013-05-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Matocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljubisa Dragoljub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC: H01L29/36 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract translation: 半导体器件包括：包含碳化硅的衬底; 设置在所述衬底上的漂移层，包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域，其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部，所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数，半导体器件的电荷容差大于1.0×1013 / cm2。

公开(公告)号：US20150008449A1

公开(公告)日：2015-01-08

申请号：US13934053

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L21/22

CPC classification number: H01L29/1608 ,  H01L21/22 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/7827

Abstract: A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer.

Abstract translation: 半导体器件包括设置在（0001）取向的SiC衬底上的碳化硅（SiC）漂移层。 SiC漂移层具有包括平行于半导体器件的沟道的长度定向的多个重复特征的非平面表面。 此外，沟道区设置在SiC漂移层的特定结晶平面中。

公开(公告)号：US11245003B2

公开(公告)日：2022-02-08

申请号：US16517193

申请日：2019-07-19

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US20210288180A1

公开(公告)日：2021-09-16

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11069772B2

公开(公告)日：2021-07-20

申请号：US16221034

申请日：2018-12-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

公开(公告)号：US11063115B2

公开(公告)日：2021-07-13

申请号：US16708001

申请日：2019-12-09

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Yang Sui

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/08 ,  H01L21/761 ,  H01L29/10 ,  H01L29/739 ,  H01L29/872

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

公开(公告)号：US20200258985A1

公开(公告)日：2020-08-13

申请号：US16789164

申请日：2020-02-12

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/745 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20200185493A1

公开(公告)日：2020-06-11

申请号：US16708001

申请日：2019-12-09

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Yang Sui

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L21/761 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.