公开(公告)号：US20060215444A1

公开(公告)日：2006-09-28

申请号：US11089688

申请日：2005-03-24

Applicant: Frederick Perner ,  Janice Nickel ,  Lung Tran

Inventor： Frederick Perner ,  Janice Nickel ,  Lung Tran

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C11/1675

Abstract: An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.

Abstract translation: 提供信息存储装置。 信息存储装置可以是包括自旋相关隧道（SDT）结或磁存储元件的电阻交叉点阵列的磁性随机存取存储器（MRAM）装置，其中字线沿着沿着SDT结的行和沿着 SDT路口的列。 本设计包括与相关联的磁存储元件串联连接的多个加热元件，每个加热元件包括二极管。 施加到磁存储元件和相关联的加热元件的电压导致反向电流流过二极管，从而从二极管产生热量并加热磁存储元件，从而有助于器件的写入功能。

公开(公告)号：US20060050552A1

公开(公告)日：2006-03-09

申请号：US10934243

申请日：2004-09-03

Applicant: Frederick Perner

Inventor： Frederick Perner

IPC: G11C11/14

CPC classification number: H01L27/228 ,  G11C11/15 ,  G11C11/16

Abstract: A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device. The method of fabricating the memory device includes fabricating a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, fabricating a second layer of MRAM memory cells over the first layer of MRAM memory cells, and fabricating a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device.

Abstract translation: 存储器件包括根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储器单元的第一层上制造的第二层MRAM存储器单元，以及与MRAM存储器的第一层相关联的公共连接 单元和有助于存储器件操作的第二层MRAM存储器单元。 制造存储器件的方法包括制造根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储单元的第一层上制造第二层MRAM存储器单元，以及制造与第一层MRAM存储单元相关联的公共连接 MRAM存储器单元的层和有助于存储器件的操作的MRAM存储器单元的第二层。

公开(公告)号：US20060007220A1

公开(公告)日：2006-01-12

申请号：US10861035

申请日：2004-06-04

Applicant: Frederick Perner

Inventor： Frederick Perner

IPC: G09G5/00

CPC classification number: G09G3/20 ,  G09G2360/142

Abstract: A light emitting device with adaptive intensity control. In a particular embodiment, there is an active display pixel providing a light. At least a portion of the provided light is incident upon a photodetector optically coupled to the display pixel, the photodetector providing an electrical feedback signal in response to the light. A feedback controlled intensity controller electrically coupled to the photodetector and an electrical switch coupled to the active display pixel are also provided. The feedback controlled intensity controller further receives an electrical reference signal. The feedback controlled intensity controller opens and closes the switch depending upon the relationship of the feedback signal to the reference signal.

Abstract translation: 具有自适应强度控制的发光器件。 在特定实施例中，存在提供光的主动显示像素。 所提供的光的至少一部分入射到光耦合到显示像素的光电检测器上，光电检测器响应于光而提供电反馈信号。 还提供电耦合到光电检测器的反馈控制强度控制器和耦合到主动显示像素的电开关。 反馈控制强度控制器还接收电参考信号。 反馈控制强度控制器根据反馈信号与参考信号的关系打开和闭合开关。

公开(公告)号：US20050195647A1

公开(公告)日：2005-09-08

申请号：US10794302

申请日：2004-03-04

Applicant: Frederick Perner

Inventor： Frederick Perner

IPC: G11C11/15 ,  G11C7/22 ,  G11C11/00 ,  G11C11/16 ,  G11C16/26 ,  H01L21/8246 ,  H01L27/105

CPC classification number: G11C11/16

Abstract: This invention provides a 1R1D block architecture magnetic memory device. In a particular embodiment, a cross-point array of resistive devices is provided. Each resistive device is paired with an isolation device. A feedback controlled control circuit is coupled to the cross-point array. The control circuit establishes an equi-potential setting within the cross-point array, and recognizes a change in current when a selected resistive device within the cross-point array is asserted to a reference state. An associated method of use is further provided.

Abstract translation: 本发明提供一种1R1D块架构磁存储器件。 在特定实施例中，提供了电阻器件的交叉点阵列。 每个电阻设备与隔离设备配对。 反馈控制控制电路耦合到交叉点阵列。 所述控制电路在所述交叉点阵列内建立等电位设置，并且当所述交叉点阵列内的所选择的电阻性设备被认定为参考状态时，识别电流的变化。 还提供了相关联的使用方法。

公开(公告)号：US06894918B2

公开(公告)日：2005-05-17

申请号：US10697367

申请日：2003-10-30

Applicant: Manish Sharma ,  Frederick Perner

Inventor： Manish Sharma ,  Frederick Perner

IPC: G06F12/16 ,  G11C11/00 ,  G11C11/15 ,  G11C11/22 ,  G11C11/404 ,  G11C11/405 ,  G11C14/00 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L43/08 ,  G11C11/25

CPC classification number: G11C14/0036 ,  G11C11/005 ,  G11C11/404 ,  G11C11/405 ,  G11C14/00

Abstract: The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.

Abstract translation: 本发明包括提供存储器备份系统的装置和方法。 存储器备份系统包括第一存储器单元和与第一存储器单元接口的非易失性存储器单元。 控制电路允许将数据写入第一存储器单元或非易失性存储单元，并且将数据从第一存储器单元或非易失性存储单元传送到第一存储单元 或非易失性存储单元。 存储器备份系统还可以包括多个第一存储器单元以及与第一存储器单元相连接的多个非易失性存储器单元。 控制电路允许将数据写入第一存储器单元或非易失性存储器单元，并且将数据从第一存储器单元或非易失性存储器单元传送到第一存储器 单元或非易失性存储单元。

公开(公告)号：US20050073881A1

公开(公告)日：2005-04-07

申请号：US10680483

申请日：2003-10-06

Applicant: Lung Tran ,  Frederick Perner

Inventor： Lung Tran ,  Frederick Perner

IPC: G11C11/15 ,  G11C11/14 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/16 ,  G11C11/1673

Abstract: A data storage device includes a cross point array of resistive memory elements and a plurality of blocking elements. The device is arranged in groups. Each group includes series-connected memory elements and a blocking element. The blocking elements are used to prevent sneak path currents from interfering with sense currents during read operations.

Abstract translation: 数据存储装置包括电阻性存储器元件的交叉点阵列和多个阻塞元件。 设备分组安排。 每个组包括串联存储器元件和阻塞元件。 阻塞元件用于在读取操作期间防止潜行路径电流干扰读出电流。

公开(公告)号：US20050047219A1

公开(公告)日：2005-03-03

申请号：US10650278

申请日：2003-08-28

Applicant: Frederick Perner ,  Anthony Holden

Inventor： Frederick Perner ,  Anthony Holden

IPC: G11C11/15 ,  G11C5/00 ,  G11C7/00 ,  G11C7/14 ,  G11C11/02 ,  G11C11/16 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/16 ,  G11C7/14

Abstract: Disclosed herein are systems and devices having memories with reference-initiated sequential sensing. In one embodiment, a reference-initiated sequential sensing method comprises: forming a first attribute measurement associated with a stored data value in a first memory element; using the first memory element to determine a decision threshold; comparing the first attribute measurement to the decision threshold to determine the stored data value in the first memory element; forming a subsequent attribute measurement associated with a stored data value in a subsequent memory element; and comparing the subsequent attribute value to the decision threshold to determine a data value stored in the subsequent memory element.

Abstract translation: 本文公开了具有参考启动的顺序感测的存储器的系统和设备。 在一个实施例中，参考发起的顺序感测方法包括：在第一存储器元件中形成与存储的数据值相关联的第一属性测量; 使用所述第一存储器元件来确定判定阈值; 将所述第一属性测量与所述判定阈值进行比较，以确定所述第一存储器元件中存储的数据值; 形成与随后的存储器元件中存储的数据值相关联的后续属性测量; 以及将所述随后的属性值与所述判定阈值进行比较，以确定存储在所述后续存储器元件中的数据值。

公开(公告)号：US06765834B2

公开(公告)日：2004-07-20

申请号：US10299288

申请日：2002-11-19

Applicant: Frederick Perner

Inventor： Frederick Perner

IPC: G11C702

CPC classification number: G11C7/06 ,  G11C11/16

Abstract: The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells. A method of the invention includes electrically connecting multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells; and sensing logic states of the multiple memory cells.

Abstract translation: 本发明包括存储单元阵列感测系统。 存储单元阵列感测系统包括位于集成电路的第一平面上的存储器单元的阵列。 存储器单元的阵列包括存储器单元组，其中每个组对应于存储器单元的行的范围。 位于与第一平面相邻的感测平面上的多个读出放大器，至少一个读出放大器与每个组相关联。 通过电连接多个存储器单元以感测属于与多个存储器单元相关联的组的放大器以及感测不属于与多个存储器单元相关联的组的放大器来同时检测多个存储器单元。 本发明的方法包括将多个存储器单元电连接到属于与多个存储器单元相关联的组的读出放大器，以及读取不属于与多个存储器单元相关联的组的放大器; 以及感测多个存储器单元的逻辑状态。

公开(公告)号：US09064568B2

公开(公告)日：2015-06-23

申请号：US14239053

申请日：2011-08-26

Applicant: Frederick Perner

Inventor： Frederick Perner

IPC: G11C11/00 ,  G11C11/34 ,  G11C13/00 ,  G11C11/15 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/15 ,  G11C11/16 ,  G11C13/0007 ,  G11C2013/0054

Abstract: A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes a transimpedance equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. A reference resistor is selectively connected to the equipotential preamplifier for setting a reference current, wherein the equipotential preamplifier is set to produce a preamplifier output voltage having a magnitude depending on whether the sense current is smaller or greater than the reference current. A voltage comparator is connected to the equipotential preamplifier to compare the preamplifier output voltage with a setup reference voltage and generate a comparator output voltage indicative of the resistance state of the resistive switching device.

Abstract translation: 用于感测交叉点阵列中的电阻式开关器件的电阻状态的读取电路利用连接到阵列中的电阻式开关器件的选定列线的跨阻抗等电位前置放大器。 等电位前置放大器提供感测电流，同时将选定的列线保持在靠近施加到阵列的未选行行的偏置电压的参考电压。 参考电阻器选择性地连接到等电位前置放大器以设置参考电流，其中等电位前置放大器被设置为产生具有取决于感测电流是小于还是大于参考电流的幅度的前置放大器输出电压。 电压比较器连接到等电位前置放大器，以将前置放大器输出电压与设置参考电压进行比较，并生成表示电阻开关器件的电阻状态的比较器输出电压。

公开(公告)号：US20150162075A1

公开(公告)日：2015-06-11

申请号：US14396331

申请日：2012-07-10

Applicant: Frederick Perner

Inventor： Frederick Perner

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C15/04 ,  G11C19/28

Abstract: A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.

Abstract translation: 列表排序静态随机存取存储器（LSSRAM）单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元和用于可选地切换LSSRAM的动态/静态（D / S）模式选择器 动态存储模式和静态存储模式之间的单元格。 所述LSSRAM单元还包括交换选择器，用于在所述交换选择器被激活时在所述动态存储模式期间与存储在相邻存储器单元中的数据交换所存储的数据;以及数据比较器，用于将所述SRAM单元中存储的数据与所述数据进行比较 存储在相邻存储单元中并且根据比较的结果激活交换选择器。