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公开(公告)号：US20150006935A1
公开(公告)日：2015-01-01
申请号：US14300942
申请日：2014-06-10
Inventor： Jin Ho HAN , Young Su KWON , Kyoung Seon SHIN , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F1/32
CPC classification number: G06F1/3275 , G06F1/3206 , G06F12/0864 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.
Abstract translation: 公开了一种能够通过控制高速缓存的功率模式来降低高速缓存的功耗的处理器及其方法。 处理器可以包括处理器核心; 存储要在处理器核心中执行的指令的高速缓存; 以及高速缓存管理部，其基于指示根据在所述处理器核心中执行的算法确定的所述处理器核心的状态的处理器操作模式来控制所述高速缓存。 因此，可以降低高速缓存的功率消耗，并且可以通过考虑处理器的操作模式来控制高速缓存的功率模式来防止处理器核心性能的劣化。
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公开(公告)号：US20140348250A1
公开(公告)日：2014-11-27
申请号：US14286822
申请日：2014-05-23
Inventor： Seunghyun CHO , Hyun Mi KIM , Kyung Jin BYUN , Nak Woong EUM
CPC classification number: H04N19/86 , H04N19/423
Abstract: Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.
Abstract translation: 提供了一种用于多个处理元件的滤波方法，用于对用于单帧图像的多个图像分区中的多个像素块进行滤波。 用于滤波像素块的方法包括：检查与图像分区边界相邻的第二边界像素块的状态，第二边界像素块是第二图像分区中的多个像素块中的一个，并且邻近第一边界像素块 第一图像分区，与图像分区边界相邻的第一边界像素块; 基于第二边界像素块的状态为第一边界像素块选择滤波区域; 并对第一边界像素块的滤波区域进行滤波。
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33.发明公开公开(公告)号：US20240112002A1
公开(公告)日：2024-04-04
申请号：US18344275
申请日：2023-06-29
Inventor： Sung Eun KIM , Tae Wook KANG , Hyuk KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE , In San JEON
Abstract: Disclosed is an interface system including a first neuron cluster that outputs a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation, and a first interface circuit that stores the first neuron data and outputs a first response, in response to the first neuron request. The first neuron cluster outputs a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response. Before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response in response to a fact that the first neuron data is stored.
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公开(公告)号：US20240036817A1
公开(公告)日：2024-02-01
申请号：US18362596
申请日：2023-07-31
Inventor： Kyuseung HAN , Kyung Jin BYUN , Sukho LEE , Jae-Jin LEE
IPC: G06F5/01 , G06F15/78 , G06F1/3234
CPC classification number: G06F5/012 , G06F15/7807 , G06F1/3234
Abstract: Disclosed is an SoC including a CPU that generates a first function signal including a first command for a first soft float function while not having a floating point operation function, a system bus, and a soft float function circuit that receives the first function signal from the CPU through the system bus, and performs a first floating point operation corresponding to the first soft float function based on the first command.
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公开(公告)号：US20230004777A1
公开(公告)日：2023-01-05
申请号：US17857602
申请日：2022-07-05
Inventor： Sung Eun KIM , Tae Wook KANG , Hyuk KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE , In San JEON
Abstract: Disclosed are a spike neural network apparatus based on a multi-encoding and an operating method thereof. The method of operating a spike neural network (SNN) apparatus that performs a multi-encoding, includes receiving an input signal by an encoding module, performing a rate coding and a temporal coding on the received input signal by the encoding module, generating an SNN input signal based on the performance result of the rate coding and the temporal coding, and transmitting the generated SNN input signal to a neuromorphic chip that performs a spike neural network (SNN) operation.
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Patent Agency Ranking
公开(公告)号：US20220109808A1
公开(公告)日：2022-04-07
申请号：US17399603
申请日：2021-08-11
Inventor： Sukho LEE , Sang Pil KIM , Young Hwan BAE , Jae-Jin LEE , Kyuseung HAN , Tae Wook KANG , Sung Eun KIM , Hyuk KIM , Kyung Hwan PARK , Hyung-IL PARK , Kyung Jin BYUN , Kwang IL OH , In Gi LIM
Abstract: Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.
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公开(公告)号：US20200092226A1
公开(公告)日：2020-03-19
申请号：US16556905
申请日：2019-08-30
Inventor： Kyuseung HAN , Sukho LEE , Jae-Jin LEE , Sang Pil KIM , Young Hwan BAE , Kyung Jin BYUN
IPC: H04L12/933 , H04L12/42
Abstract: Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.
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38.发明申请公开(公告)号：US20180293935A1
公开(公告)日：2018-10-11
申请号：US15766464
申请日：2017-01-25
Inventor： Woo Joo LEE , Suk Ho LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: G09G3/3208 , H05B33/08 , G06F1/32 , G06F3/14
Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.
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公开(公告)号：US20170255554A1
公开(公告)日：2017-09-07
申请号：US15241902
申请日：2016-08-19
Inventor： Jin Ho HAN , Young-Su KWON , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F12/0811 , G06F12/0842 , G06F12/0875 , G06F12/084
CPC classification number: G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2212/6042 , G06F2212/62
Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.
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公开(公告)号：US20170255520A1
公开(公告)日：2017-09-07
申请号：US15241808
申请日：2016-08-19
Inventor： Jin Ho HAN , Young-Su KWON , Kyoung Seon SHIN , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F11/10 , G06F12/0895 , G06F12/0804
CPC classification number: G06F11/1076 , G06F12/0804 , G06F12/0808 , G06F12/0864 , G06F12/0895 , G06F12/0897 , G06F2212/1032
Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.
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