公开(公告)号：US20140143495A1

公开(公告)日：2014-05-22

申请号：US13946112

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method of partitioning a data cache comprising a plurality of sets, the plurality of sets comprising a plurality of ways, is provided. Responsive to a stack data request, the method stores a cache line associated with the stack data in one of a plurality of designated ways of the data cache, wherein the plurality of designated ways is configured to store all requested stack data.

Abstract translation: 提供了一种分割包括多个集合的数据高速缓存的方法，所述多个集合包括多个方式。 响应于堆栈数据请求，该方法将与堆栈数据相关联的高速缓存行存储在数据高速缓存的多个指定方式之一中，其中多个指定路径被配置为存储所有请求的堆栈数据。

公开(公告)号：US10133678B2

公开(公告)日：2018-11-20

申请号：US14012475

申请日：2013-08-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Syed Ali Jafri ,  Srilatha Manne ,  Gabriel Loh

IPC: G06F12/00 ,  G06F12/126

Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.

公开(公告)号：US09734059B2

公开(公告)日：2017-08-15

申请号：US13945659

申请日：2013-07-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/123 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0862

CPC classification number: G06F12/0802 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

公开(公告)号：US20170220022A1

公开(公告)日：2017-08-03

申请号：US15010965

申请日：2016-01-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Can Hankendi ,  Manish Arora ,  Indrain Paul ,  Wei Huang ,  Srilatha Manne

IPC: G05B19/404

CPC classification number: G06F1/206

Abstract: A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.

公开(公告)号：US09524164B2

公开(公告)日：2016-12-20

申请号：US14015282

申请日：2013-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F9/312 ,  G06F9/345 ,  G06F9/52 ,  G06F12/08 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0875

Abstract: A system and method for efficient predicting and processing of memory access dependencies. A computing system includes control logic that marks a detected load instruction as a first type responsive to predicting the load instruction has high locality and is a candidate for store-to-load (STL) data forwarding. The control logic marks the detected load instruction as a second type responsive to predicting the load instruction has low locality and is not a candidate for STL data forwarding. The control logic processes a load instruction marked as the first type as if the load instruction is dependent on an older store operation. The control logic processes a load instruction marked as the second type as if the load instruction is independent on any older store operation.

Abstract translation: 一种用于有效预测和处理内存访问依赖关系的系统和方法。 计算系统包括控制逻辑，其将检测到的加载指令标记为响应于预测加载指令具有高局部性并且是存储到加载（STL）数据转发的候选者的第一类型。 控制逻辑将检测到的加载指令标记为响应于预测加载指令具有低局部性而不是STL数据转发的候选的第二类型。 控制逻辑处理标记为第一类型的加载指令，就像加载指令取决于较旧的存储操作一样。 控制逻辑处理标记为第二类型的加载指令，就像加载指令独立于任何较旧的存储操作一样。

公开(公告)号：US09442557B2

公开(公告)日：2016-09-13

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。

公开(公告)号：US09378153B2

公开(公告)日：2016-06-28

申请号：US14011616

申请日：2013-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Syed Ali Jafri ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/127 ,  G06F12/0804 ,  G06F12/123 ,  Y02D10/13

Abstract: A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. The modified data is stored in the set in a cache line with an eviction priority that is at least as high as an eviction priority, before the modified data is stored, of an unmodified cache line with a highest eviction priority among unmodified cache lines in the set.

Abstract translation: 一级高速缓冲存储器从更高级别的缓存存储器接收修改的数据。 识别具有与修改的数据相关联的索引的一组高速缓存行。 修改后的数据被存储在高速缓存行中，其具有在修改数据被存储之前至少与驱逐优先级一样高的驱逐优先级，该缓存优先级在未修改的高速缓存行中具有最高驱逐优先级的未修改高速缓存行 组。

公开(公告)号：US20160085219A1

公开(公告)日：2016-03-24

申请号：US14493189

申请日：2014-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Manish Arora ,  Yasuko Eckert ,  Srilatha Manne

IPC: G05B15/02 ,  G06N5/04

CPC classification number: G06N5/04 ,  G06F1/206 ,  G06F1/329 ,  G06F9/4893 ,  Y02D10/24

Abstract: A processing device includes a plurality of components and a system management unit to selectively schedule an application phase to one of the plurality of components based on one or more comparisons of predictions of a plurality of thermal impacts of executing the application phase on each of the plurality of components. The predictions may be generated based on a thermal history associated with the application phase, thermal sensitivities of the plurality of components, or a layout of the plurality of components in the processing device.

Abstract translation: 一种处理设备包括多个组件和系统管理单元，用于基于对多个组件中的每一个上执行应用阶段的多个热冲击的预测的一个或多个比较来选择性地将应用阶段调度到多个组件之一 的组件。 可以基于与应用阶段相关联的热历史，多个组件的热敏感性或处理设备中的多个组件的布局来生成预测。

公开(公告)号：US09294263B2

公开(公告)日：2016-03-22

申请号：US14146654

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Buckler ,  Wayne P. Burleson ,  Srilatha Manne

IPC: H04J3/06 ,  H04L7/02 ,  G06F1/12 ,  H04W56/00 ,  H04L7/033

CPC classification number: H04L7/02 ,  G06F1/12 ,  H04J3/0602 ,  H04J3/0632 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0331 ,  H04W56/001

Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Abstract translation: 电路包括多个同步器，用于将来自第一时钟域的信号适配到第二时钟域。 多个同步器的每个同步器包括用于接收来自第一时钟域的信号的同步器输入和同步器输出以提供适合于第二时钟域的信号。 该电路还包括多路复用器（多路复用器），其包括多个多路复用器输入和多路复用器输出。 每个多路复用器输入耦合到多个同步器的相应同步器的同步器输出端。 多路复用器输出从多个同步器的所选同步器的同步器输出提供适应于第二时钟域的信号。

公开(公告)号：US20160049181A1

公开(公告)日：2016-02-18

申请号：US14460550

申请日：2014-08-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Syed Ali Jafri ,  Yasuko Eckert ,  Srilatha Manne ,  Mithuna S. Thottethodi

IPC: G11C7/10 ,  G06F12/10 ,  G11C11/406

CPC classification number: G06F12/1009 ,  G06F2212/1024 ,  G06F2212/654 ,  G06F2212/655 ,  G06F2212/656

Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.

Abstract translation: 描述了通过分析对虚拟存储器页面的存储器绑定访问的序列，确定所访问的虚拟存储器页面之间的连续程度以及访问的虚拟存储器页面的映射集合来将虚拟存储器页面映射到物理存储器页面的方法和系统的实施例 存储页面到相应的单个物理存储器页面。 还描述了用于通过分析虚拟存储器访问的模式以识别所访问的虚拟存储器页的邻接性，基于该模式来预测所访问的虚拟存储器页的邻接性的方法来增加虚拟存储器系统中对DRAM的存储器访问的局部性的方法，以及 将所识别的和预测的连续虚拟存储器页面映射到相应的单个物理存储器页面。