公开(公告)号：US20240088147A1

公开(公告)日：2024-03-14

申请号：US18152007

申请日：2023-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED ,  TSMC CHINA COMPANY, LIMITED

发明人： XinYong WANG ,  Cun Cun CHEN ,  Ying HUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/092 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5286

摘要： An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

公开(公告)号：US20240088128A1

公开(公告)日：2024-03-14

申请号：US18518706

申请日：2023-11-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： Yang ZHOU ,  Liu HAN ,  Qingchao MENG ,  XinYong WANG ,  ZeJian CAI

IPC分类号： H01L27/02 ,  G06F30/392 ,  H01L21/265 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092

CPC分类号： H01L27/0207 ,  G06F30/392 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76898 ,  H01L21/823892 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0928 ,  H01L2225/06513 ,  H01L2225/06541

摘要： A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.

公开(公告)号：US20240056062A1

公开(公告)日：2024-02-15

申请号：US17822559

申请日：2022-08-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Huaixin XIAN ,  Longbiao LEI ,  Sinpei GOA ,  Zhang-Ying YAN ,  Qingchao MENG ,  Jerry Chang Jui KAO

IPC分类号： H03K3/86 ,  H03K3/037 ,  H03K3/356

CPC分类号： H03K3/86 ,  H03K3/0375 ,  H03K3/356113

摘要： A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.

公开(公告)号：US11893334B2

公开(公告)日：2024-02-06

申请号：US17875139

申请日：2022-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

发明人： Yi-Lin Chuang ,  Shi-Wen Tan ,  Song Liu ,  Shih-Yao Lin ,  Wen-Yuan Fang

IPC分类号： G06F30/00 ,  G06F30/392 ,  G06F30/373 ,  G06F30/398 ,  G06F30/394

CPC分类号： G06F30/392 ,  G06F30/373 ,  G06F30/394 ,  G06F30/398

摘要： A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.

公开(公告)号：US11843382B2

公开(公告)日：2023-12-12

申请号：US17736913

申请日：2022-05-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： Jing Ding ,  Zhang-Ying Yan ,  Qingchao Meng ,  Lei Pan

IPC分类号： H03K3/037 ,  G06F30/392 ,  H03K19/0185

CPC分类号： H03K3/037 ,  G06F30/392 ,  H03K19/018521

摘要： A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

公开(公告)号：US11838026B2

公开(公告)日：2023-12-05

申请号：US17362305

申请日：2021-06-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Huaixin Xian ,  Liu Han ,  Jing Ding ,  Qingchao Meng

IPC分类号： H03K5/135 ,  G06F1/04 ,  G06F30/392 ,  H03K3/037 ,  H03K17/687 ,  G06F117/04

CPC分类号： H03K5/135 ,  G06F1/04 ,  G06F30/392 ,  H03K3/037 ,  H03K17/6872 ,  G06F2117/04

摘要： An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.

公开(公告)号：US20230387129A1

公开(公告)日：2023-11-30

申请号：US18362868

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

发明人： Tian-Yu XIE ,  Xin-Yong WANG ,  Lei PAN ,  Kuo-Ji CHEN

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L21/76283 ,  H01L29/78

摘要： An IC structure includes first and second gates, first and second source regions, a shared drain region, and an isolation region. The first gate has a first portion extending along a first direction and a second portion extending along a second direction. The second gate has a first portion extending along the first direction and a second portion extending along the second direction. The shared drain region extends from the first portion of the first gate to the first portion of the second gate. The first source region is spaced apart from the shared drain region by the first gate. The second source region is spaced apart from the shared drain region by the second gate. The isolation region is between the first portion of the first gate and the first portion of the second gate, and resembles a quadrilateral pattern bordering the shared drain region.

公开(公告)号：US20230376660A1

公开(公告)日：2023-11-23

申请号：US18356426

申请日：2023-07-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Ankita PATIDAR ,  Sandeep Kumar GOEL ,  Yun-Han LEE

IPC分类号： G06F30/327 ,  G06F30/398

CPC分类号： G06F30/327 ,  G06F30/398 ,  G06F2119/18

摘要： A method includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group has a unique dominant feature among a plurality of features of the plurality of paths. The method further includes testing a path in a group and, when the path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. The plurality of features includes a numerical feature having a numerical value, and a categorical feature having a non-numerical value. The non-numerical value is converted into a converted numerical value. The plurality of groups is created based on the numerical value of the numerical feature, and the converted numerical value of the categorical feature.

公开(公告)号：US20230368828A1

公开(公告)日：2023-11-16

申请号：US18354445

申请日：2023-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED ,  TSMC NANJING COMPANY, LIMITED

发明人： XiuLi YANG ,  Ching-Wei WU ,  He-Zhou WAN ,  Kuan CHENG ,  Luping KONG

IPC分类号： G11C8/18 ,  G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C8/18 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C11/419

摘要： A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.

公开(公告)号：US11784646B1

公开(公告)日：2023-10-10

申请号：US17830601

申请日：2022-06-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Ying Huang ,  Changlin Huang ,  Jing Ding ,  Qingchao Meng

IPC分类号： H03K19/0185 ,  G06F30/392 ,  G06F119/06

CPC分类号： H03K19/018521 ,  G06F30/392 ,  G06F2119/06

摘要： An integrated circuit (IC) device includes first and second power rails extending in a first direction, a third power rail extending in the first direction between the first and second power rails, gate structures extending perpendicular to the first direction, each of two endmost gate structures extending continuously between endpoints underlying the first and second power rails, and first through fourth pluralities of active areas extending in the first direction between the endmost gate structures. Active areas of each of the first through fourth pluralities of active areas are aligned in the first direction, a first portion of the gate structures and first through fourth pluralities of active areas is configured as a functional circuit, and a second portion of the gate structures and first through fourth pluralities of active areas is configured as one of a decoupling capacitor or an antenna diode.