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公开(公告)号:US20180097566A1
公开(公告)日:2018-04-05
申请号:US15564924
申请日:2015-11-11
Applicant: Sanechips Technology Co., Ltd.
IPC: H04B10/2507 , H04J14/02
CPC classification number: H04B10/2507 , G02B6/2861 , G02F1/353 , H04J14/02
Abstract: Disclosed are a strong filter compensation method and device, and a computer storage medium. The method includes filtering out a high-frequency noise by delay summation; determining a correct path from one or more interference item paths; and comprehensively analyzing the determined correct path for every data input during a pre-set period of time, taking the correct path which has the largest number of occurrences as a final correct path, and outputting data in the path.
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公开(公告)号:US09935595B2
公开(公告)日:2018-04-03
申请号:US15306340
申请日:2014-10-08
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor: Dong Wei , Weisheng Geng
CPC classification number: H03F3/2171 , H02M1/14 , H02M3/155 , H02M2001/0025 , H03F1/303 , H03F3/005 , H03F3/2178 , H03F2200/351 , H03F2200/78
Abstract: Disclosed is a switch control circuit, including an error amplifier, a compensation network and a control circuit, wherein the compensation network is connected to an output end of the error amplifier; and the control circuit includes switches from a first switch to a fifth switch and is configured to control operating states of the error amplifier and the compensation network by controlling on/off states of switches from the first switch to the fifth switch. Further disclosed are switch control method, a regulator including the above switch control circuit as well as a computer storage medium.
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公开(公告)号:US09930630B2
公开(公告)日:2018-03-27
申请号:US14916728
申请日:2014-05-22
Applicant: Sanechips Technology Co., Ltd.
Inventor: Zhongwei Liu , Qinxin Li , Ning Qiu , Yannan Xing , Qianchao Gan
CPC classification number: H04W56/001 , G01S5/02 , G01S5/0205 , H04L5/0048 , H04W52/04 , H04W64/00 , H04W72/0446
Abstract: The present disclosure discloses a method and device for determining a position, and a computer storage medium. The method includes that a first power value for a SYNC-NL segment within a DwPTS, a second power value for a first GP segment which precedes the SYNC-NL segment, a third power value for a second GP segment which follows the SYNC-NL segment, and a fourth power value for a time slot 0 are acquired; an eigenvalue of the DwPTS is calculated according to the first power value, the second power value, the third power value and the fourth power value; and the position of the DwPTS is determined according to the eigenvalue.
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公开(公告)号:US20180081836A1
公开(公告)日:2018-03-22
申请号:US15565176
申请日:2015-09-09
Applicant: Sanechips Technology Co.,Ltd.
Inventor: Bo Wen
CPC classification number: G06F13/28 , G06F5/065 , G06F2205/067
Abstract: A direct memory access (DMA) controller and method are disclosed. The DMA controller comprises: a read data channel input interface, a write data channel output interface, a control logic module, a first-in-first-out (FIFO) module, and comprises: a first converter for performing first operation processing on first data read from external memory via the read data channel input interface; a first data selector for strobing the data processed by the first converter when it is judged that there is a need to perform data operation, and then writing the processed data into the FIFO module; a second converter for performing second operation processing on second data read from the FIFO module; and a second data selector for strobing the data processed by the second converter when it is judged that there is a need to perform data operation, and then outputting the processed data to the write data channel output interface.
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公开(公告)号:US09907036B2
公开(公告)日:2018-02-27
申请号:US15035464
申请日:2014-05-19
Applicant: Sanechips Technology Co.,Ltd.
Inventor: Gang Feng
IPC: H04W56/00 , H04L1/00 , H04L12/801 , H04L12/863 , H04W72/04
CPC classification number: H04W56/00 , H04L1/0079 , H04L47/34 , H04L47/625 , H04W72/0446
Abstract: Disclosed is a multipath time division service transmission method, comprising: calculating a channel service serial number corresponding to the time division service of each path, determining, according to the calculated channel service serial number, the channel number (CN) of a channel having service data transmission, and respectively and sequentially writing the service data and CN of the channel having service data transmission into a service data first input first output (FIFO) and a service channel index (CI) FIFO; and correspondingly, in order to read a service, respectively reading from the service data FIFO and the service CI FIFO the service data of the time division service and the CN of the channel transmitting the same. Also disclosed is a transmission device of a multipath time division service.
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公开(公告)号:US09866240B2
公开(公告)日:2018-01-09
申请号:US15322331
申请日:2014-09-15
Applicant: Sanechips Technology Co., Ltd.
Inventor: Xi Wang , Ning Qiu , Nanshan Cao
CPC classification number: H03M7/30 , H03M13/2957 , H03M13/3972
Abstract: An MAP algorithm-based Turbo decoding method and apparatus. The method includes: iteratively estimating an information symbol by using an MAP algorithm, acquiring an α and β window boundary values of each sliding window by means of window boundary value inheritance, acquiring an α block boundary value and β block boundary value of each sub-block by means of block boundary value inheritance, and recursively calculating posterior probability Log Likelihood Ratio (LLR) values of a whole window and a whole block according to the α boundary values and the β boundary values (101); and performing decoding decision according to the LLR values (102).
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公开(公告)号:US20170294903A1
公开(公告)日:2017-10-12
申请号:US15511795
申请日:2014-12-15
Applicant: Sanechips Technology Co., Ltd.
Inventor: Maosheng Xia , Qing Zhang
IPC: H03K5/135
CPC classification number: H03K5/135 , G06F1/08 , G06F1/12 , H03K5/1252
Abstract: Disclosed are a dynamic clock switching method and apparatus as well as a computer readable medium. The apparatus comprises a clock selection signal generation unit, a clock enable signal generation unit, a synchronization unit and a gating unit; the clock selection signal generation unit is configured to generate two or more clock selection signals and transmit same to the clock enable signal generation unit; the clock enable signal generation unit is configured to generate a clock enable signal based on a plurality of clock selection signals transmitted by the clock selection signal generation unit and transmit the clock enable signal to the synchronization unit; the synchronization unit is configured to synchronize the clock enable signal and transmit the synchronized clock enable signal to the gating unit; and the gating unit is configured to open or close the output of the clock signal based on the clock enable signal synchronized by the synchronization unit.
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公开(公告)号:US20170279937A1
公开(公告)日:2017-09-28
申请号:US15504123
申请日:2014-11-18
Applicant: Sanechips Technology Co., Ltd.
Inventor: Sheng Shi , Quan Sun , Junhua Yan
IPC: H04L29/06 , H04L29/12 , H04L12/749
CPC classification number: H04L69/167 , H04L12/4633 , H04L45/74 , H04L45/741 , H04L61/1511 , H04L61/251 , H04L61/2542 , H04L61/6013 , H04L67/2823
Abstract: A method for the translation between IPv4 and IPv6 is disclosed, including: a BIH link tracker and quick translator are provided in a network core and when a link is established between an IPv4 client and IPv6 server, a standard translator translates and sends to the IPv6 server, a packet sent from the IPv4 client to the IPv6 server, and theBIH link tracker extracts and records information on link and translation of the IPv4 client and IPv6 server from the packet for interaction therebetween; and during a process of sending the packet after establishing the link between the IPv4 client and IPv6 server, the packet is sent to the quick translator which translates and sends the packet according to the information on the translation corresponding to the information on the link recorded by the BIH link tracker. A device for the translation between IPv4 and IPv6 is also disclosed.
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公开(公告)号:US20170279266A1
公开(公告)日:2017-09-28
申请号:US15505646
申请日:2015-01-19
Applicant: SANECHIPS TECHNOLOGY CO., LTD
Inventor: Xiang Yu , Xinfu Zhou
IPC: H02H7/26 , B60Q11/00 , H02H3/38 , H02H7/08 , G08B13/196
CPC classification number: H02H7/262 , B60Q11/00 , G01R22/06 , G06F1/3206 , G06F1/3212 , G06F11/3062 , G06Q10/00 , G08B13/19634 , H02H3/382 , H02H7/0844 , H04W52/0254 , Y02D10/34 , Y02D70/00
Abstract: Disclosed an electricity amount detection method and device, a terminal and a storage medium. The method includes that: Identity (ID) information of each function device called by an application is acquired according to ID information of the application; a power consumption parameter generated when each function device is called is correspondingly acquired according to the ID information of each function device called by the application; a power consumption parameter generated when the application is running is determined according to the power consumption parameter generated by each function device; and the power consumption parameter generated when the application is running is output as a power consumption index when the application is running.
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40.
公开(公告)号:US20170155458A1
公开(公告)日:2017-06-01
申请号:US15323322
申请日:2014-10-31
Applicant: Sanechips Technology Co.,Ltd.
Inventor: Kaijiang He , Junfeng Peng
CPC classification number: H04J3/0658 , H04L1/0083 , H04L25/14 , H04L69/22
Abstract: Disclosed are a multi-lane synchronization method and apparatus. The method includes: forming N data frames, frame headers of the N data frames including an identical frame header sequence, N being greater than or equal to 1 and less than or equal to the number of lanes M, and M being an integer not less than 2; and sending the N data frames via N lanes, wherein different data frames are sent via different lanes, and the frame header sequence is configured to perform frame synchronization between a receiving end and a sending end or to check frame synchronization. Also disclosed are a synchronization system and a computer storage medium.
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