DMA CONTROLLER, IMPLEMENTATION METHOD AND COMPUTER STORAGE MEDIUM

    公开(公告)号:US20180081836A1

    公开(公告)日:2018-03-22

    申请号:US15565176

    申请日:2015-09-09

    Inventor: Bo Wen

    CPC classification number: G06F13/28 G06F5/065 G06F2205/067

    Abstract: A direct memory access (DMA) controller and method are disclosed. The DMA controller comprises: a read data channel input interface, a write data channel output interface, a control logic module, a first-in-first-out (FIFO) module, and comprises: a first converter for performing first operation processing on first data read from external memory via the read data channel input interface; a first data selector for strobing the data processed by the first converter when it is judged that there is a need to perform data operation, and then writing the processed data into the FIFO module; a second converter for performing second operation processing on second data read from the FIFO module; and a second data selector for strobing the data processed by the second converter when it is judged that there is a need to perform data operation, and then outputting the processed data to the write data channel output interface.

    Multipath time division service transmission method and device

    公开(公告)号:US09907036B2

    公开(公告)日:2018-02-27

    申请号:US15035464

    申请日:2014-05-19

    Inventor: Gang Feng

    Abstract: Disclosed is a multipath time division service transmission method, comprising: calculating a channel service serial number corresponding to the time division service of each path, determining, according to the calculated channel service serial number, the channel number (CN) of a channel having service data transmission, and respectively and sequentially writing the service data and CN of the channel having service data transmission into a service data first input first output (FIFO) and a service channel index (CI) FIFO; and correspondingly, in order to read a service, respectively reading from the service data FIFO and the service CI FIFO the service data of the time division service and the CN of the channel transmitting the same. Also disclosed is a transmission device of a multipath time division service.

    Map algorithm-based turbo decoding method and apparatus, and computer storage medium

    公开(公告)号:US09866240B2

    公开(公告)日:2018-01-09

    申请号:US15322331

    申请日:2014-09-15

    CPC classification number: H03M7/30 H03M13/2957 H03M13/3972

    Abstract: An MAP algorithm-based Turbo decoding method and apparatus. The method includes: iteratively estimating an information symbol by using an MAP algorithm, acquiring an α and β window boundary values of each sliding window by means of window boundary value inheritance, acquiring an α block boundary value and β block boundary value of each sub-block by means of block boundary value inheritance, and recursively calculating posterior probability Log Likelihood Ratio (LLR) values of a whole window and a whole block according to the α boundary values and the β boundary values (101); and performing decoding decision according to the LLR values (102).

    DYNAMIC CLOCK SWITCHING METHOD AND APPARATUS AS WELL AS COMPUTER READABLE MEDIUM

    公开(公告)号:US20170294903A1

    公开(公告)日:2017-10-12

    申请号:US15511795

    申请日:2014-12-15

    CPC classification number: H03K5/135 G06F1/08 G06F1/12 H03K5/1252

    Abstract: Disclosed are a dynamic clock switching method and apparatus as well as a computer readable medium. The apparatus comprises a clock selection signal generation unit, a clock enable signal generation unit, a synchronization unit and a gating unit; the clock selection signal generation unit is configured to generate two or more clock selection signals and transmit same to the clock enable signal generation unit; the clock enable signal generation unit is configured to generate a clock enable signal based on a plurality of clock selection signals transmitted by the clock selection signal generation unit and transmit the clock enable signal to the synchronization unit; the synchronization unit is configured to synchronize the clock enable signal and transmit the synchronized clock enable signal to the gating unit; and the gating unit is configured to open or close the output of the clock signal based on the clock enable signal synchronized by the synchronization unit.

    METHOD AND DEVICE FOR TRANSLATION BETWEEN IPV4 AND IPV6

    公开(公告)号:US20170279937A1

    公开(公告)日:2017-09-28

    申请号:US15504123

    申请日:2014-11-18

    Abstract: A method for the translation between IPv4 and IPv6 is disclosed, including: a BIH link tracker and quick translator are provided in a network core and when a link is established between an IPv4 client and IPv6 server, a standard translator translates and sends to the IPv6 server, a packet sent from the IPv4 client to the IPv6 server, and theBIH link tracker extracts and records information on link and translation of the IPv4 client and IPv6 server from the packet for interaction therebetween; and during a process of sending the packet after establishing the link between the IPv4 client and IPv6 server, the packet is sent to the quick translator which translates and sends the packet according to the information on the translation corresponding to the information on the link recorded by the BIH link tracker. A device for the translation between IPv4 and IPv6 is also disclosed.

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