公开(公告)号：US20170140087A1

公开(公告)日：2017-05-18

申请号：US15322420

申请日：2014-11-18

Applicant: Sanechips Technology Co.,Ltd.

Inventor： Qing Zhang ,  Chongxing Gao

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5045 ,  G06F2217/06

Abstract: A method for chip integration is disclosed. The method includes: inputting the parameter file information of a parameter file required to be searched; obtaining a sub-module port list according to the input parameter file information; carrying out the connection between module ports and/or sub-module ports according to the obtained sub-module port list and a pre-configured netlist; and generating a top level file according to the connection between the module ports and/or the sub-module ports, so as to realize the chip integration. A device for chip integration and a storage medium are disclosed as well.

公开(公告)号：US20170294903A1

公开(公告)日：2017-10-12

申请号：US15511795

申请日：2014-12-15

Applicant: Sanechips Technology Co., Ltd.

Inventor： Maosheng Xia ,  Qing Zhang

IPC: H03K5/135

CPC classification number: H03K5/135 ,  G06F1/08 ,  G06F1/12 ,  H03K5/1252

Abstract: Disclosed are a dynamic clock switching method and apparatus as well as a computer readable medium. The apparatus comprises a clock selection signal generation unit, a clock enable signal generation unit, a synchronization unit and a gating unit; the clock selection signal generation unit is configured to generate two or more clock selection signals and transmit same to the clock enable signal generation unit; the clock enable signal generation unit is configured to generate a clock enable signal based on a plurality of clock selection signals transmitted by the clock selection signal generation unit and transmit the clock enable signal to the synchronization unit; the synchronization unit is configured to synchronize the clock enable signal and transmit the synchronized clock enable signal to the gating unit; and the gating unit is configured to open or close the output of the clock signal based on the clock enable signal synchronized by the synchronization unit.