公开(公告)号：US20180081836A1

公开(公告)日：2018-03-22

申请号：US15565176

申请日：2015-09-09

Applicant: Sanechips Technology Co.,Ltd.

Inventor： Bo Wen

IPC: G06F13/28 ,  G06F5/06

CPC classification number: G06F13/28 ,  G06F5/065 ,  G06F2205/067

Abstract: A direct memory access (DMA) controller and method are disclosed. The DMA controller comprises: a read data channel input interface, a write data channel output interface, a control logic module, a first-in-first-out (FIFO) module, and comprises: a first converter for performing first operation processing on first data read from external memory via the read data channel input interface; a first data selector for strobing the data processed by the first converter when it is judged that there is a need to perform data operation, and then writing the processed data into the FIFO module; a second converter for performing second operation processing on second data read from the FIFO module; and a second data selector for strobing the data processed by the second converter when it is judged that there is a need to perform data operation, and then outputting the processed data to the write data channel output interface.

公开(公告)号：US10481957B2

公开(公告)日：2019-11-19

申请号：US15763996

申请日：2016-07-01

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Bo Wen ,  Qingxin Cao

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/48 ,  G06F9/38

Abstract: A processor and a task processing method therefor, and a storage medium. The method comprises: a scalar calculation module executing parameter calculation of a current task, and storing a parameter obtained through calculation in a PBUF; when the parameter calculation of the current task is completed, executing a first instruction or second instruction for inter-core synchronization, and storing the first instruction or the second instruction in the PBUF (301); a vector calculation module reading the parameter from the PBUF, storing the read parameter in a shadow register; when the first instruction or the second instruction is read from the PBUF, storing all the modified parameters in the shadow register in a work register within a period (302); and the vector calculation module executing vector calculation of the current task according to the parameter in the work register (303).

公开(公告)号：US20180276051A1

公开(公告)日：2018-09-27

申请号：US15763996

申请日：2016-07-01

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Bo Wen ,  Qingxin Cao

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/30

CPC classification number: G06F9/52 ,  G06F9/30036 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3889 ,  G06F9/4881

Abstract: A processor and a task processing method therefor, and a storage medium. The method comprises: a scalar calculation module executing parameter calculation of a current task, and storing a parameter obtained through calculation in a PBUF; when the parameter calculation of the current task is completed, executing a first instruction or second instruction for inter-core synchronization, and storing the first instruction or the second instruction in the PBUF (301); a vector calculation module reading the parameter from the PBUF, storing the read parameter in a shadow register; when the first instruction or the second instruction is read from the PBUF, storing all the modified parameters in the shadow register in a work register within a period (302); and the vector calculation module executing vector calculation of the current task according to the parameter in the work register (303).