知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

177 条记录 (耗时 0.043 秒)

    Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
    31.
    发明授权
    Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.) 有权
    具有数据流处理器和具有两维或多维可编程单元结构（FPGA，DPGAs等）的模块的配置数据的分级缓存方法

    公开(公告)号：US06687788B2

    公开(公告)日：2004-02-03

    申请号：US10191926

    申请日：2002-07-09

    申请人： Martin Vorbach ,  Robert Münch

    发明人： Martin Vorbach ,  Robert Münch

    IPC分类号： G06F1200

    CPC分类号： G06F15/7867 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084

    摘要： A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a group, and connecting the cache unit to a higher level unit via a tree structure. The cache unit may send requests for required commands to the higher level cache unit, which may return a command sequence including the required command, if the higher level cache unit holds the first command sequence including the required command in the higher level cache unit's local memory.

    摘要翻译： 提供了一种在具有多个算术单元的微处理器中以及具有两维或多维单元布置的模块中缓存命令的方法。 该方法包括组合多个单元和算术单元以形成多个组，将高速缓存单元分配给组，以及经由树结构将高速缓存单元连接到较高级单元。 高速缓存单元可以向上级高速缓存单元发送所需命令的请求，如果较高级别的高速缓存单元在上级高速缓存单元的本地存储器中保存包括所需命令的第一命令序列，则可以返回包括所需命令的命令序列 。

    Method of self-synchronization of configurable elements of a programmable module
    34.
    再颁专利
    Method of self-synchronization of configurable elements of a programmable module 有权

    公开(公告)号：USRE45109E1

    公开(公告)日：2014-09-02

    申请号：US12909203

    申请日：2010-10-21

    申请人： Martin Vorbach ,  Robert M. Munch

    发明人： Martin Vorbach ,  Robert M. Munch

    IPC分类号： G06F15/16

    CPC分类号： G06F15/7867

    摘要： A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.

    Reconfigurable elements
    36.
    发明授权
    Reconfigurable elements 有权
    可重构元素

    公开(公告)号：US08686475B2

    公开(公告)日：2014-04-01

    申请号：US13023796

    申请日：2011-02-09

    申请人： Martin Vorbach

    发明人： Martin Vorbach

    IPC分类号： H01L27/10

    CPC分类号： G06F9/30036 ,  G06F9/30014 ,  G06F9/3887 ,  G06F15/17375 ,  G06F15/7842

    摘要： A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

    摘要翻译： 描述用于具有用于执行代数和/或逻辑功能的功能单元和用于接收，存储和/或输出信息的存储单元的数据处理的单元元素字段。 控制连接可能会从功能单元导向存储单元。

    PARALLEL MEMORY SYSTEMS
    37.
    发明申请
    PARALLEL MEMORY SYSTEMS 审中-公开
    并行存储系统

    公开(公告)号：US20140052961A1

    公开(公告)日：2014-02-20

    申请号：US14000155

    申请日：2012-02-17

    申请人： Martin Vorbach

    发明人： Martin Vorbach

    IPC分类号： G06F15/78

    CPC分类号： G06F15/7839 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/38 ,  G06F15/7821 ,  G06F2213/0038 ,  G11C8/16 ,  G11C11/412 ,  Y02D10/12 ,  Y02D10/13

    摘要： The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.

    摘要翻译： 本发明涉及一种多核处理器存储器系统，其中提供了该系统包括多核处理器和系统存储器之间的存储器通道，并且该系统至少包括与处理器核心一样多的存储器通道，每个存储器 专用于处理器核心的通道，并且存储器系统在运行时将动态地专用于访问核心的存储器块相关联，访问内核经由存储器通道具有对存储体的专用访问。

    Method of self-synchronization of configurable elements of a programmable module
    39.
    再颁专利
    Method of self-synchronization of configurable elements of a programmable module 有权
    可编程模块的可配置元件的自同步方法

    公开(公告)号：USRE44383E1

    公开(公告)日：2013-07-16

    申请号：US12109280

    申请日：2008-04-24

    申请人： Martin Vorbach ,  Robert M. Münch

    发明人： Martin Vorbach ,  Robert M. Münch

    IPC分类号： G06F15/16

    CPC分类号： G06F15/7867

    摘要： A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.

    摘要翻译： 提供了一种在可编程单元中同步和重新配置可配置元件的方法。 单元具有二维或多维可编程单元架构（例如，DFP，DPGA等），并且任何可配置元件可以通过互连架构访问其他可配置元件的配置寄存器和状态寄存器，并且 因此可以对其功能和操作产生积极的影响。 通过同步每个元素的责任，可以同时执行更多的同步任务，因为独立元素在访问中央同步实例时不再彼此干扰。