公开(公告)号：US20110310667A1

公开(公告)日：2011-12-22

申请号：US13219980

申请日：2011-08-29

Applicant: Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

Inventor： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract translation: 半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括 多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且 使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度 其他在字线方向。

公开(公告)号：US08077523B2

公开(公告)日：2011-12-13

申请号：US12406382

申请日：2009-03-18

Applicant: Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

Inventor： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/08

Abstract: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

Abstract translation: 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

公开(公告)号：US08069357B2

公开(公告)日：2011-11-29

申请号：US12122267

申请日：2008-05-16

Applicant: Hiroshi Nakamura ,  Masaaki Kondo ,  Takashi Nanya ,  Ryo Watanabe

Inventor： Hiroshi Nakamura ,  Masaaki Kondo ,  Takashi Nanya ,  Ryo Watanabe

IPC: G06F1/26

CPC classification number: G06F1/32

Abstract: A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit.

Abstract translation: 根据本发明的示例的多处理器控制设备包括协作控制单元，其确定从处理器向共享资源发出的请求的优先级，所述共享资源用于在所述处理器的性能约束的范围内抑制所述处理器的总功耗 满足处理器执行的程序，并且确定每个处理器的频率，以便抑制在满足每个节目的性能约束的范围内的总功耗;发出来自处理器的请求的第一控制单元 根据由协作控制单元确定的优先级来分配给共享资源;以及第二控制单元，其根据由协作控制单元确定的频率来控制每个处理器的频率。

公开(公告)号：US20110286268A1

公开(公告)日：2011-11-24

申请号：US13193968

申请日：2011-07-29

Applicant: Makoto Iwai ,  Hiroshi Nakamura

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Abstract translation: 存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线 到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并且产生大于所选择的读取电位的未被选择的读取电位的电位产生电路， 以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。

公开(公告)号：US08055260B2

公开(公告)日：2011-11-08

申请号：US12208788

申请日：2008-09-11

Applicant: Keiji Machida ,  Hironari Kobayashi ,  Hiroshi Nakamura

Inventor： Keiji Machida ,  Hironari Kobayashi ,  Hiroshi Nakamura

IPC: H04W4/00

CPC classification number: H04W8/06 ,  H04W8/08

Abstract: The unnecessarily increase of the information amount of subscriber information retained by a local subscriber information management device is prevented even if the number of subscribers increases, so that the limit of the number of subscribers is extended to support the increasing number of subscribers without increasing the capacity of subscriber information retaining means in the local station (local subscriber information management device). Based on information contained in subscriber management information 211, 221 including information representing each mobile terminal 310, 320 acquired by local stations 210, 220 of a mobile communication system 100 and subscriber information corresponding to each mobile terminal 310, 320, the relevant subscriber management information 211, 221 are selected and processed to be prevented from being retained after call control is performed according to the acquired subscriber management information.

Abstract translation: 即使用户数量增加，也防止了本地用户信息管理装置所保留的用户信息的信息量的不必要的增加，从而扩大了用户数量的限制，以支持越来越多的用户而不增加容量 在本地站（本地用户信息管理设备）中的用户信息保留装置。 基于包含在用户管理信息211,221中的信息，包括表示由移动通信系统100的本地站210,220获取的每个移动终端310,320的信息和对应于每个移动终端310,320的用户信息的相关用户管理信息 211,221根据获取的用户管理信息进行呼叫控制之后被选择和处理以防止保留。

公开(公告)号：US20110220721A1

公开(公告)日：2011-09-15

申请号：US13044903

申请日：2011-03-10

Applicant: Hiroshi NAKAMURA

Inventor： Hiroshi NAKAMURA

IPC: G06K7/14

CPC classification number: G06K7/14 ,  G06K7/1439 ,  G06K7/1452 ,  G06K7/1465 ,  G06K7/1473 ,  G06K7/1486

Abstract: Provided is a method and an apparatus for reading barcode information; the method and apparatus being able to read barcode information correctly without being influenced by the environmental conditions at the time of reading the barcode information. When a reading method according to a prescribed rule could not read a character, each element width is judged again to be either thin or thick according to structural characteristics of characters to convert again an element width matrix into a bit pattern, and then a character corresponding to the bit pattern as a result of the re-conversion is determined.

Abstract translation: 提供了一种用于读取条形码信息的方法和装置; 该方法和装置能够在读取条形码信息时不受环境条件的影响而正确地读取条形码信息。 当根据规定的规则的读取方法不能读取字符时，根据字符的结构特征再次将每个元素宽度再次判断为粗或粗，以将元素宽度矩阵再次转换为位模式，然后将字符对应 确定作为重新转换的结果的位模式。

公开(公告)号：US20110195663A1

公开(公告)日：2011-08-11

申请号：US12931139

申请日：2011-01-25

Applicant: Takahiro Sakai ,  Jun Tada ,  Hiroyuki Nagasawa ,  Hiroshi Nakamura

Inventor： Takahiro Sakai ,  Jun Tada ,  Hiroyuki Nagasawa ,  Hiroshi Nakamura

IPC: H04B7/00

CPC classification number: H04L12/66 ,  G06Q10/00 ,  G06Q30/0207 ,  H04L67/02 ,  H04L67/04 ,  H04M1/7253 ,  H04M1/72561

Abstract: There is provided a mobile terminal including: a contactless communication unit transmitting an IC identifier to a reader-writer that carries out contactless communication and receiving link information including the IC identifier from the reader-writer; and a wireless communication unit accessing a server based on the link information, transmitting the link information to the server, transmitting the IC identifier to the server separately to the link information, and operable, when the server has judged based on the IC identifier that contactless communication with the reader-writer and access to the server were both carried out using a same mobile terminal owned by a user, to receive information relating to privilege available to the user on a service used by the user from the server apparatus.

Abstract translation: 提供了一种移动终端，包括：非接触式通信单元，其向执行非接触式通信的读写器发送IC标识符，并从读写器接收包括IC标识符的链接信息; 以及基于所述链接信息访问服务器的无线通信单元，向所述服务器发送所述链接信息，将所述IC标识符分别发送到所述服务器与所述链接信息，并且当所述服务器基于所述IC标识符判断为非接触式 使用与用户拥有的相同的移动终端进行与读写器的通信和对服务器的访问，以便从服务器装置接收用户使用的服务上接收与用户有关的特权的信息。

公开(公告)号：US07996011B2

公开(公告)日：2011-08-09

申请号：US12036838

申请日：2008-02-25

Applicant: Masaru Takahashi ,  Hiroshi Nakamura

Inventor： Masaru Takahashi ,  Hiroshi Nakamura

IPC: H04W36/00

CPC classification number: H04W28/08 ,  H04W36/14 ,  H04W88/06 ,  H04W88/16

Abstract: Data is transmitted through a plurality of types of communication networks to a mobile communication terminal while a handover of the mobile communication terminal is handled. A communication control apparatus 10 is adapted to control data communication to a cell phone 50 connectable to a plurality of types of communication networks, and is composed of a detecting unit 12 for detecting a connection status of the cell phone 50 in each mobile communication network; an assigning unit 13 for assigning data addressed to the cell phone 50, to each mobile communication network to which the cell phone 50 is connected, based on a volume of the data addressed to the cell phone 50 and the detected connection status; a transmitting unit 15 for transmitting the data assigned to each mobile communication network, to the each mobile communication network; and a handover processing unit 14 for performing a handover process in the plurality of types of mobile communication networks, based on the detected connection status.

Abstract translation: 在处理移动通信终端的切换的同时，将数据通过多种类型的通信网络发送到移动通信终端。 通信控制装置10适于控制与可连接到多种通信网络的蜂窝电话50的数据通信，并且由用于检测移动通信网络中的蜂窝电话50的连接状态的检测单元12构成。 基于指向蜂窝电话50的数据量和检测到的连接状态，分配单元13，用于将寻址到蜂窝电话50的数据分配给与蜂窝电话50连接的每个移动通信网络; 发送单元15，用于将分配给每个移动通信网络的数据发送到每个移动通信网络; 以及切换处理单元14，用于基于检测到的连接状态来执行多种类型的移动通信网络中的切换处理。

公开(公告)号：US07940562B2

公开(公告)日：2011-05-10

申请号：US12689786

申请日：2010-01-19

Applicant: Hiroshi Nakamura ,  Tomoharu Tanaka

Inventor： Hiroshi Nakamura ,  Tomoharu Tanaka

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/30

Abstract: A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.

Abstract translation: 非挥发性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元 单元格阵列。 在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未选择的字线。 将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二 写入中间电压。

公开(公告)号：US20110075488A1

公开(公告)日：2011-03-31

申请号：US12960882

申请日：2010-12-06

Applicant: Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

Inventor： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

Abstract translation: 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。