公开(公告)号：US09394953B2

公开(公告)日：2016-07-19

申请号：US14123260

申请日：2012-05-31

Applicant: Takanori Kato ,  Takahiro Fujimoto ,  Kazutaka Asabe ,  Atsushi Sakaguchi ,  Yasushi Karino ,  Shin-ichi Saga ,  Takashi Maejima ,  Satoru Nakano ,  Takeshi Nakano

Inventor： Takanori Kato ,  Takahiro Fujimoto ,  Kazutaka Asabe ,  Atsushi Sakaguchi ,  Yasushi Karino ,  Shin-ichi Saga ,  Takashi Maejima ,  Satoru Nakano ,  Takeshi Nakano

IPC: F16D65/092 ,  F16D55/22 ,  B61H5/00

CPC classification number: F16D55/22 ,  B61H5/00 ,  F16D65/092

Abstract: A disc brake for railway vehicles includes a brake disc fixed to a wheel or an axle of a railway vehicle and a brake lining configured to be pressed against a frictional surface of the brake disc by a brake caliper. The brake lining includes a plurality of friction members arranged to be spaced from each other, each of the friction members having a surface that faces the frictional surface of the brake disc, a metallic backing secured to back surfaces of the friction members, and a base plate supporting the friction members on the back surface side via spring members. The base plate is mounted to a brake caliper; wherein the friction members are provided in pairs with each pair being formed by two adjacent ones of the friction members, and the metallic backing is a one-piece member provided for each pair of the friction members.

Abstract translation: 轨道车辆的盘式制动器包括固定到铁路车辆的车轮或车轴的制动盘和构造成通过制动钳压在制动盘的摩擦表面上的制动衬片。 制动衬片包括多个彼此分开设置的摩擦构件，每个摩擦构件具有面向制动盘的摩擦表面的表面，固定到摩擦构件的后表面的金属背衬和基座 板经由弹簧构件支撑背面侧的摩擦构件。 基板安装在制动钳上; 其中摩擦构件成对设置，每对摩擦构件由两个相邻的摩擦构件形成，并且金属背衬是为每对摩擦构件设置的单件构件。

公开(公告)号：US08335125B2

公开(公告)日：2012-12-18

申请号：US13285099

申请日：2011-10-31

Applicant: Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

Inventor： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

IPC: G11C8/00

CPC classification number: G11C16/08

Abstract: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

Abstract translation: 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

公开(公告)号：US08250447B2

公开(公告)日：2012-08-21

申请号：US12158966

申请日：2006-12-21

Applicant: Mitsuharu Senda ,  Youhei Murakami ,  Takeshi Nakano ,  Masamitsu Nishikido

Inventor： Mitsuharu Senda ,  Youhei Murakami ,  Takeshi Nakano ,  Masamitsu Nishikido

IPC: G06F11/00

CPC classification number: H03M13/235

Abstract: A bit register is restored to the initial state thereof irrespective of the state of the bit register even when a convolution encoder includes a circular section.The convolution encoder comprises an input data acquiring section (F11) for acquiring input data; an encoding object data generating section (F10) for generating encoding object data on the basis of the input data; a storage section (M10) for storing data corresponding to the encoding object data; a mod2 adder (S10) for performing convolution processing of the encoding object data on the basis of the data stored in the storage section (M10); and a switching section (F12) for switching at a prescribed timing the encoding object data generated by the encoding object data generating section (F10) from data based on the input data to data based on the data stored in the storage section (M10); wherein the data stored in the storage section (M10) are data obtained as a result of the convolution processing.

Abstract translation: 即使当卷积编码器包括圆形部分时，位寄存器也恢复到初始状态，而与位寄存器的状态无关。 卷积编码器包括用于获取输入数据的输入数据获取部分（F11）; 编码对象数据生成部（F10），用于根据输入数据生成编码对象数据; 用于存储对应于编码对象数据的数据的存储部分（M10）; mod2加法器（S10），用于根据存储在存储部分中的数据（M10）进行编码对象数据的卷积处理; 以及切换部（F12），用于根据存储在存储部（M10）中的数据，将由编码对象数据生成部（F10）生成的编码对象数据，基​​于输入数据的数据切换到规定的定时。 其中存储在存储部分（M10）中的数据是作为卷积处理的结果获得的数据。

公开(公告)号：US20100329017A1

公开(公告)日：2010-12-30

申请号：US12822587

申请日：2010-06-24

Applicant: Takeshi NAKANO ,  Mikio Ogawa

Inventor： Takeshi NAKANO ,  Mikio Ogawa

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.

Abstract translation: 根据一个实施例，半导体器件包括第一电压发生器，第二电压发生器，第一MOS晶体管和控制器。 第一电压发生器向第一节点输出第一电压。 第二电压发生器向第二节点输出第二电压。 第一MOS晶体管能够使第一节点和第二节点短路。 控制器通过接通第一MOS晶体管来执行控制操作以使第一节点和第二节点短路。 控制器基于时间控制第一MOS晶体管保持在接通状态的时段。

公开(公告)号：US20100098997A1

公开(公告)日：2010-04-22

申请号：US12523814

申请日：2008-01-11

Applicant: Hiroyuki Ohgi ,  Tomohiro Ono ,  Shinji Nakai ,  Takeshi Nakano ,  Takeshi Kusudou ,  Naoki Fujiwara

Inventor： Hiroyuki Ohgi ,  Tomohiro Ono ,  Shinji Nakai ,  Takeshi Nakano ,  Takeshi Kusudou ,  Naoki Fujiwara

IPC: H01M8/10

CPC classification number: H01B1/122 ,  C08F8/12 ,  C08F293/005 ,  C08F2220/585 ,  C08F2800/20 ,  C08J5/2231 ,  C08J2331/04 ,  C08J2333/26 ,  C08J2387/00 ,  H01M8/1032 ,  H01M8/1067 ,  H01M8/1088 ,  H01M2300/0082 ,  Y02P70/56 ,  C08F218/08

Abstract: A polymer electrolyte membrane comprising as a main ingredient a block copolymer (P) which comprises, as its constituents, a vinyl alcoholic polymer block (A) and a polymer block (B) having ion-conducting groups, which block copolymer(P) is cross-linking treated, and a membrane-electrode assembly and a fuel cell using the polymer electrolyte membrane, respectively. Preferred as polymer block (B) is one having a styrene or vinylnaphthalene skeleton or a 2-(meth)acrylamido-2-methylpropane skeleton. The ion-conducting group includes a sulfonic acid group, a phosphonic acid group or the like.

Abstract translation: 一种聚合物电解质膜，其包含嵌段共聚物（P）作为主要成分，所述嵌段共聚物（P）包含乙烯基醇聚合物嵌段（A）和具有离子传导性基团的聚合物嵌段（B）作为其组分，所述嵌段共聚物（P）为 交联处理，以及分别使用聚合物电解质膜的膜 - 电极组件和燃料电池。 聚合物嵌段（B）优选具有苯乙烯或乙烯基萘骨架或2-（甲基）丙烯酰胺基-2-甲基丙烷骨架。 离子传导性基团包括磺酸基，膦酸基等。

公开(公告)号：US20090243272A1

公开(公告)日：2009-10-01

申请号：US12411067

申请日：2009-03-25

Applicant: Masaaki Tanaka ,  Katsuyuki Komiya ,  Shin Murata ,  Norihisa Adachi ,  Yukihito Itami ,  Hitoshi Nagai ,  Takeshi Nakano

Inventor： Masaaki Tanaka ,  Katsuyuki Komiya ,  Shin Murata ,  Norihisa Adachi ,  Yukihito Itami ,  Hitoshi Nagai ,  Takeshi Nakano

IPC: B62D21/06

CPC classification number: B60G3/202 ,  B60G7/02 ,  B60G99/00 ,  B60G2200/18 ,  B60G2200/182 ,  B60G2204/15 ,  B60G2206/60 ,  B62D21/11

Abstract: Disclosed is a suspension subframe structure of a vehicle, which is capable of improving the overall rigidity of a suspension subframe to effectively receive input loads from suspension arms, while reducing the overall weight of the suspension subframe. The suspension subframe structure for supporting a plurality of suspension arms 14, 16 of a multi-link suspension system comprises first and second lateral members 20, 22 each extending in a lateral direction of the vehicle body, a pair of longitudinal members each extending in a longitudinal direction of the vehicle body, and right and left inclined members 28 each having one end which is located on the side of a respective one of right and left ends of the first lateral member and provided with an upper-arm support portion and a lower-arm support portion, wherein each of the right and left inclined members extends obliquely relative to the lateral direction in top plan view to connect the upper-arm support portion and the lower-arm support portion with a laterally intermediate portion of the second lateral member.

Abstract translation: 公开了一种车辆的悬架子框架结构，其能够提高悬架子框架的总体刚度，以有效地从悬架臂接收输入载荷，同时减小悬架子系统的总重量。 用于支撑多连杆悬架系统的多个悬挂臂14,16的悬架子框架结构包括第一和第二横向构件20,22，每个横向构件沿着车身的横向方向延伸，一对纵向构件，每个纵向构件以 车体的纵向方向以及左右的倾斜部件28，所述左右的倾斜部件28的一端位于第一侧面部件的左右两端的一侧，并且具有上臂支撑部和下部 臂支撑部分，其中左右倾斜构件中的每一个在俯视图中相对于横向方向倾斜地延伸，以将上臂支撑部分和下臂支撑部分与第二横向构件的横向中间部分连接 。

公开(公告)号：US20080005530A1

公开(公告)日：2008-01-03

申请号：US11767756

申请日：2007-06-25

Applicant: Takeshi Nakano

Inventor： Takeshi Nakano

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G11C29/76

Abstract: A semiconductor memory device has a semiconductor memory which includes the first central management block storing an address translation table, a free table for registering only an effective block address, the first bad block table, and a reserved table, and a controller configured to control a substitution block address acquired from the reserved table to substitute a bad block address when the bad block address is generated in the address translation table.

Abstract translation: 半导体存储器件具有半导体存储器，其包括存储地址转换表的第一中央管理块，仅注册有效块地址的空闲表，第一坏块表和保留表，以及控制器， 当在地址转换表中生成坏块地址时，从保留表获取的替换块地址替换坏块地址。

公开(公告)号：US07238563B2

公开(公告)日：2007-07-03

申请号：US10793923

申请日：2004-03-08

Applicant: Norihisa Arai ,  Takeshi Nakano ,  Koki Ueno ,  Akira Shimizu

Inventor： Norihisa Arai ,  Takeshi Nakano ,  Koki Ueno ,  Akira Shimizu

IPC: H01L21/336

CPC classification number: H01L21/823481 ,  H01L21/2652 ,  H01L21/76237 ,  H01L29/0619 ,  H01L29/78

Abstract: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

Abstract translation: 沟槽隔离区域形成在半导体衬底的表面区域中以形成MOS型元件区域。 具有开口部的掩模层形成在半导体层上，开口部在MOS型元件区域的整个表面和设置在MOS型元件区域周围的沟槽隔离区域的一部分上连续地范围。 通过掩模层将第一杂质离子注入整个表面，以形成杂质分布的峰位于浅沟槽隔离区的底表面下的半导体层中。 通过掩模层将第二杂质离子注入整个表面以形成杂质分布的峰位于沟槽隔离区的深度方向的中间。 然后，第一和第二杂质离子被激活。

公开(公告)号：US06275444B1

公开(公告)日：2001-08-14

申请号：US09255779

申请日：1999-02-23

Applicant: Takeshi Nakano ,  Kazunari Takahashi

Inventor： Takeshi Nakano ,  Kazunari Takahashi

IPC: G11C800

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222

Abstract: A semiconductor integrated circuit is disclosed which includes a clock synchronous memory, an internal clock generating circuit, a clock selecting circuit, a data output converting circuit, and a data output selecting circuit. The clock synchronous memory is disposed to receive a control signal, an address signal, and a data input and provide an internal data output. The internal clock generating circuit is disposed to generate an internal clock signal having a frequency higher than that of an external clock signal. The clock selecting circuit is disposed to select between the external clock signal and the internal clock signal and send the selected clock signal to the clock synchronous memory. The data output converting circuit is disposed to convert the internal data output into an external data output in synchronization with a clock signal having a frequency lower than that of the internal clock signal. The data output selecting circuit is disposed to select between the internal data output and the external data output and provide the selected data output.

Abstract translation: 公开了一种半导体集成电路，其包括时钟同步存储器，内部时钟发生电路，时钟选择电路，数据输出转换电路和数据输出选择电路。 时钟同步存储器被设置为接收控制信号，地址信号和数据输入并提供内部数据输出。 内部时钟发生电路被设置为产生具有高于外部时钟信号的频率的内部时钟信号。 时钟选择电路被设置为在外部时钟信号和内部时钟信号之间进行选择，并将选择的时钟信号发送到时钟同步存储器。 数据输出转换电路被设置成与具有低于内部时钟信号的频率的时钟信号同步地将内部数据输出转换成外部数据输出。 数据输出选择电路被设置为在内部数据输出和外部数据输出之间进行选择，并提供所选择的数据输出。

公开(公告)号：US5463016A

公开(公告)日：1995-10-31

申请号：US193887

申请日：1994-02-09

Applicant: Isao Tomioka ,  Takeshi Nakano ,  Mikio Furukawa ,  Yoshiaki Echigo

Inventor： Isao Tomioka ,  Takeshi Nakano ,  Mikio Furukawa ,  Yoshiaki Echigo

IPC: B29C55/02 ,  B29K79/00 ,  C08G73/10 ,  C08J3/12 ,  C08J3/14 ,  C08L79/08 ,  C09D179/08 ,  H01B3/30 ,  C08G77/10 ,  C08G69/26

CPC classification number: C08G73/1032 ,  C08J3/12 ,  C08J3/14 ,  C08J2379/08

Abstract: This invention provides (1) a granular material of a polyimide precursor, which has excellent solubility in solvents and excellent moldability and from which a polyimide molding having excellent mechanical properties can be produced, (2) a mixture of a granular material of a polyimide precursor with a solvent, in which the polyimide precursor shows excellent storage stability and (3) a process for the production of a granular material of a polyimide precursor, in which a solvent can be easily removed. Particularly provided are a polyimide precursor granular material having an intrinsic viscosity of 0.7 or higher and a polyimide precursor mixture which consists of a polyimide precursor granular polyimide having an intrinsic viscosity of 0.7 or higher and a solvent that does not exhibit a strong-mutual interaction with the polyimide precursor, as well as a process for the production of the polyimide precursor granular material. The granular material of a polyimide precursor can be obtained by allowing a tetracarboxylic dianhydride to undergo polymerization reaction with a diamine in a solvent that does not exhibit a strong mutual interaction with the polyimide precursor.

Abstract translation: 本发明提供（1）聚酰亚胺前体的粒状材料，其在溶剂中的溶解性优异，成型性优异，可以制造出具有优异的机械性能的聚酰亚胺成型体，（2）聚酰亚胺前体的粒状材料 与聚酰亚胺前体显示优异的储存稳定性的溶剂和（3）可以容易地除去溶剂的聚酰亚胺前体的粒状材料的制造方法。 特别提供特性粘度为0.7以上的聚酰亚胺前体粒状材料和由特性粘度为0.7以上的聚酰亚胺前体粒状聚酰亚胺构成的聚酰亚胺前体混合物和不显示与 聚酰亚胺前体，以及聚酰亚胺前体粒状材料的制造方法。 聚酰亚胺前体的粒状材料可以通过使四羧酸二酐与不与聚酰亚胺前体表现出强相互作用的溶剂中的二胺进行聚合反应来获得。