公开(公告)号：US07474125B2

公开(公告)日：2009-01-06

申请号：US11635004

申请日：2006-12-07

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H03K19/20 ,  H03K19/094

CPC classification number: H03K19/0941 ,  H01L27/098 ,  H01L29/66901 ,  H01L29/808 ,  H03K2217/0018

Abstract: A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

Abstract translation: 提供了一种使用具有小线宽的一对互补结场效应晶体管（CJFET）的逆变器的方法。 该方法包括使所述CJFET反相器的输入电容小于类似线宽的CMOS反相器的对应输入电容。 与所述CMOS反相器相比，CJFET工作在比具有降低的开关功率的正向偏置二极管的电压降低的电源，并且具有至少与相应延迟相当的所述CJFET反相器的传播延迟 的CMOS反相器。

公开(公告)号：US20080232157A1

公开(公告)日：2008-09-25

申请号：US12109329

申请日：2008-04-24

Applicant: Ashok Kumar KAPOOR

Inventor： Ashok Kumar KAPOOR

IPC: G11C5/14

CPC classification number: G11C11/4023 ,  G11C11/404 ,  G11C11/412 ,  G11C16/0416 ,  H01L27/1104

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM and NVM devices.

Abstract translation: 在深亚微米存储器阵列中，注意到电流值相对稳定，因此减小了包括存储器单元的晶体管的阈值。 这又导致存储单元的漏电流的增加。 随着使用越来越多的存储单元，必须控制漏电流。 公开了具有动态阈值电压控制方案的随机存取存储器，其不再对现有的MOS工艺技术进行微小的改变。 所公开的发明控制MOS晶体管的阈值电压。 还包括用于增强使用该装置的动态阈值控制技术的影响的方法。 本发明对SRAM，DRAM和NVM器件特别有用。

公开(公告)号：US09147459B2

公开(公告)日：2015-09-29

申请号：US12610895

申请日：2009-11-02

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H01L29/94 ,  H01L27/108 ,  G11C11/402 ,  G11C11/404 ,  G11C11/412 ,  G11C16/04 ,  H01L27/11

CPC classification number: G11C11/4023 ,  G11C11/404 ,  G11C11/412 ,  G11C16/0416 ,  H01L27/1104

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices.

Abstract translation: 在深亚微米存储器阵列中，注意到电流值相对稳定，因此减小了包括存储器单元的晶体管的阈值。 这又导致存储单元的漏电流的增加。 随着使用越来越多的存储单元，必须控制漏电流。 公开了具有动态阈值电压控制方案的随机存取存储器，其不再对现有的MOS工艺技术进行微小的改变。 所公开的发明控制MOS晶体管的阈值电压。 还包括用于增强使用该装置的动态阈值控制技术的影响的方法。 本发明对DRAM和NVM器件特别有用。

公开(公告)号：US08048732B2

公开(公告)日：2011-11-01

申请号：US12701896

申请日：2010-02-08

Applicant: Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kumar Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H01L21/8238

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract translation: 公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。 根据本发明的装置可在低于2V的电压下工作。 这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。 使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。 该方案控制每个晶体管的阈值电压。 在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。 在ON状态下，阈值电压的大小减小，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

公开(公告)号：US07941098B2

公开(公告)日：2011-05-10

申请号：US11824737

申请日：2007-07-02

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H04B7/00

CPC classification number: G06F13/4004 ,  H04L27/12 ,  H04L27/148

Abstract: A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit.

Abstract translation: 公开了一种包括共享公共数据线和方法的发射机电路和接收机电路的半导体器件。 每个发射机电路可以包括接收数据流并且以预定载波频率提供频率调制数据输出的频率调制器。 每个接收机可以包括带通滤波器，其允许从相应的发射机电路输出的对应的频率调制数据通过到解调器，同时基本排除其它调频数据。 以这种方式，多个发射机电路可以同时将多个发射机电路中的每一个发送数据的数据发送到预定的接收机电路。

公开(公告)号：US07651905B2

公开(公告)日：2010-01-26

申请号：US11110457

申请日：2005-04-19

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/28052 ,  H01L29/4916 ,  H01L29/665 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/909

Abstract: An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.

Abstract translation: 公开了一种用于减少深亚微米金属氧化物半导体（MOS）晶体管中的栅极泄漏的装置和方法，特别适用于交叉耦合的静态随机存取存储器（SRAM）单元中使用的那些。 根据本发明，SRAM单元的有源元件用于降低其晶体管栅极上的电压，而不影响电路的开关速度。 由于反相器输出的负载是固定的，所以优化了栅极电流的减小以最小化对存储器单元的开关波形的影响。 由具有不同费米电位的两种材料形成的有源元件用作整流结或二极管。 整流结还具有大的并联泄漏路径，当在该器件上施加相反极性的信号时，允许有限电流流动。

公开(公告)号：US20090174464A1

公开(公告)日：2009-07-09

申请号：US12348797

申请日：2009-01-05

Applicant: Ashok Kumar Kapoor ,  Robert Strain

Inventor： Ashok Kumar Kapoor ,  Robert Strain

IPC: H03K3/01 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/66636 ,  H01L29/7833 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Abstract translation: 使用正向偏置二极管来减少在绝缘体上硅（SOI）上实现的晶体管的泄漏电流是一个特别的挑战，因为难以实现与晶体管栅极之下的区域的有效接触。 通过与晶体管外部的区域接触的隧道在源极下方的SOI栅极指中的改进的实现。 另一实施例使用漏极延伸植入物来提供良好的通道连接。

公开(公告)号：US20090142889A1

公开(公告)日：2009-06-04

申请号：US12276574

申请日：2008-11-24

Applicant: Madhukar B. Vora ,  Ashok Kumar Kapoor

Inventor： Madhukar B. Vora ,  Ashok Kumar Kapoor

IPC: H01L21/337

CPC classification number: H01L29/808 ,  H01L29/66901

Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

Abstract translation: 具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。 小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。 金属沉积在所述电介质层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。 一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。

公开(公告)号：US20080014687A1

公开(公告)日：2008-01-17

申请号：US11484402

申请日：2006-07-11

Applicant: Madhukar B. Vora ,  Ashok Kumar Kapoor

Inventor： Madhukar B. Vora ,  Ashok Kumar Kapoor

IPC: H01L21/337

CPC classification number: H01L29/808 ,  H01L29/66901

Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

Abstract translation: 具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。 小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。 金属沉积在所述电介质层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。 一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。