公开(公告)号：US07863695B2

公开(公告)日：2011-01-04

申请号：US12200599

申请日：2008-08-28

申请人： Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

发明人： Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/26506 ,  H01L21/31155 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/785

摘要： A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.

摘要翻译： 互补半导体器件包括半导体衬底，形成在半导体衬底的表面上的第一半导体区域，形成在半导体衬底的离开第一半导体区域的表面上的第二半导体区域，具有第一栅极的n-MIS晶体管 形成在第一半导体区域上的包括La和Al的绝缘膜和形成在栅极绝缘膜上的第一栅电极和形成在第二半导体区上的具有包括La和Al的第二栅极绝缘膜的p-MIS晶体管， 以及形成在所述栅极绝缘膜上的第二栅电极，所述第二栅极绝缘膜中的原子密度比Al / La大于所述第一栅极绝缘膜中的原子密度比Al / La。

公开(公告)号：US20100065886A1

公开(公告)日：2010-03-18

申请号：US12482054

申请日：2009-06-10

申请人： Yoshiki KAMATA ,  Akira TAKASHIMA

发明人： Yoshiki KAMATA ,  Akira TAKASHIMA

IPC分类号： H01L29/78 ,  H01L21/335

CPC分类号： H01L29/24 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/785

摘要： According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括：衬底，其包括以Ge为主要成分的半导体区域; 形成在半导体区域上方的包含Ge并且具有非金属特性的化合物层; 形成在化合物层上方的绝缘膜; 形成在绝缘膜上的电极; 以及形成在基板中以将电极夹在其间的源极/漏极区域。

公开(公告)号：US20090315659A1

公开(公告)日：2009-12-24

申请号：US12213749

申请日：2008-06-24

申请人： Shinichi Sato ,  Satoshi Kurimoto ,  Makoto Morita ,  Akira Takashima ,  Sumio Takahashi ,  Yoshiaki Kitajima

发明人： Shinichi Sato ,  Satoshi Kurimoto ,  Makoto Morita ,  Akira Takashima ,  Sumio Takahashi ,  Yoshiaki Kitajima

IPC分类号： H01F27/29 ,  H01F7/06

CPC分类号： H01F17/045 ,  H01F27/027 ,  H01F27/292 ,  H01F27/327 ,  H01F2027/065 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49174

摘要： A coil component having an easily discernible orientation, and a method of producing such a coil component that facilitates the injection of resin. A coil component includes a core with a winding portion, first and second flanges disposed on either end of the winding portion, and a winding accommodating region defined by the winding portion and the first and second flanges, terminal electrodes disposed on the second flange and a winding wound about the winding portion and connected to the terminal electrodes. An insulating resin is formed over the winding at the winding accommodating region. A marker made from a material the same as the insulating resin is provided at outer peripheral surface of the flanges.

摘要翻译： 具有容易识别的取向的线圈部件，以及制造有助于树脂注入的这种线圈部件的方法。 线圈部件包括具有绕组部分的芯部，布置在绕组部分的任一端上的第一和第二凸缘以及由绕组部分和第一和第二凸缘限定的绕组容纳区域，设置在第二凸缘上的端子电极和 缠绕在绕组部分上并连接到端子电极。 在卷绕容纳区域的绕组上形成绝缘树脂。 由与绝缘树脂相同的材料制成的标记设置在凸缘的外周面上。

公开(公告)号：US20090107586A1

公开(公告)日：2009-04-30

申请号：US12051286

申请日：2008-03-19

申请人： Akira TAKASHIMA ,  Koichi Muraoka

发明人： Akira TAKASHIMA ,  Koichi Muraoka

IPC分类号： C23C8/10

CPC分类号： C23C14/08 ,  C23C14/24 ,  C23C14/50 ,  C23C14/564 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645

摘要： A method for manufacturing a lanthanum oxide compound on a substrate includes: setting the number of H2O molecule, the number of CO molecule and the number of CO2 molecule to one-half or less, one-fifth or less and one-tenth or less per one lanthanum atom, respectively, the H2O molecule, the CO molecule and the CO2 molecule being originated from an H2O gas component, a CO gas component and a CO2 gas component in an atmosphere under manufacture; and supplying a metal raw material containing at least one selected from the group consisting of lanthanum, aluminum, titanium, zirconium and hafnium and an oxygen raw material gas simultaneously for the substrate under the condition that the number of O2 molecule are set to 20 or more per one lanthanum atom, thereby manufacturing the lanthanum oxide compound on the substrate.

摘要翻译： 在基材上制造氧化镧化合物的方法包括：将H 2 O分子的数量，CO分子的数目和CO 2分子的数量设定为每分钟的一半以下，五分之一以下，十分之一以下 一个镧原子分别来自制造气氛中的H 2 O分子，CO分子和CO 2分子源自H 2 O气体组分，CO气体组分和CO 2气体组分; 在氧分子数为20以上的条件下，向基板供给含有选自镧，铝，钛，锆，铪和氧原料气体中的至少一种的金属原料 每一个镧原子，从而在基底上制造氧化镧化合物。

公开(公告)号：US20090057750A1

公开(公告)日：2009-03-05

申请号：US12049875

申请日：2008-03-17

申请人： Akira TAKASHIMA ,  Shoko Kikuchi ,  Koichi Muraoka

发明人： Akira TAKASHIMA ,  Shoko Kikuchi ,  Koichi Muraoka

IPC分类号： H01L29/00

CPC分类号： H01L29/7881 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/792

摘要： A nonvolatile semiconductor memory element includes a semiconductor substrate, a source region and a drain region which are provided separately in the semiconductor substrate, a tunnel insulating layer which is provided between the source region and the drain region on the semiconductor substrate, a charge storage layer which is provided on the tunnel insulating layer, a block insulating layer which is provided on the charge storage layer and includes a crystallized lanthanum aluminate layer, and a control gate electrode which is provided on the block insulating layer.

摘要翻译： 非易失性半导体存储元件包括分别设置在半导体衬底中的半导体衬底，源极区域和漏极区域，设置在半导体衬底上的源极区域和漏极区域之间的隧道绝缘层，电荷存储层 其设置在隧道绝缘层上，块状绝缘层设置在电荷存储层上，并且包含结晶的铝酸镧层，以及设置在块绝缘层上的控制栅电极。

公开(公告)号：US20080211011A1

公开(公告)日：2008-09-04

申请号：US12024297

申请日：2008-02-01

申请人： Akira TAKASHIMA ,  Kouichi Muraoka

发明人： Akira TAKASHIMA ,  Kouichi Muraoka

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L29/685

摘要： It is made possible to provide a nonvolatile semiconductor memory element that can be miniaturized and can store multi-level data. A nonvolatile semiconductor memory element includes a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; and a gate structure formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region. The gate structure includes a tunnel insulating layer, a resistance variable layer formed above the tunnel insulating layer and made of a metal oxide, and a first electrode formed on the resistance variable layer.

摘要翻译： 可以提供可以小型化并且可以存储多级数据的非易失性半导体存储元件。 非易失性半导体存储元件包括半导体衬底; 在半导体衬底中形成为彼此间隔一定距离的源极区域和漏极区域; 以及形成在半导体衬底的一部分上的栅极结构，该部分位于源极区和漏极区之间。 栅极结构包括隧道绝缘层，形成在隧道绝缘层上方并由金属氧化物构成的电阻变化层，以及形成在电阻变化层上的第一电极。

公开(公告)号：US20060226529A1

公开(公告)日：2006-10-12

申请号：US11448863

申请日：2006-06-08

申请人： Yoshiharu Kato ,  Satoru Kawamoto ,  Fumihiko Taniguchi ,  Tetsuya Hiraoka ,  Akira Takashima

发明人： Yoshiharu Kato ,  Satoru Kawamoto ,  Fumihiko Taniguchi ,  Tetsuya Hiraoka ,  Akira Takashima

IPC分类号： H01L23/02

CPC分类号： H01L22/22 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/8513 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

公开(公告)号：US20060214217A1

公开(公告)日：2006-09-28

申请号：US11224049

申请日：2005-09-13

申请人： Hiroshi Watanabe ,  Atsuhiro Kinoshita ,  Akira Takashima ,  Daisuke Hagishima

发明人： Hiroshi Watanabe ,  Atsuhiro Kinoshita ,  Akira Takashima ,  Daisuke Hagishima

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.

公开(公告)号：US06960827B2

公开(公告)日：2005-11-01

申请号：US10817808

申请日：2004-04-06

申请人： Takao Nishimura ,  Tadashi Uno ,  Hiroshi Onodera ,  Akira Takashima

发明人： Takao Nishimura ,  Tadashi Uno ,  Hiroshi Onodera ,  Akira Takashima

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L23/34

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00

摘要： A stacked-type semiconductor device has a reduced overall height and an improved reliability in the mechanical strength of the stacked structure. The semiconductor device also has an improved heat release characteristic. A first interposer has a surface on which first electrode pads are formed and a first semiconductor element is mounted with a circuit forming surface facing the first interposer. A second interposer has a surface on which second electrode pads are formed and a second semiconductor element is mounted with a circuit forming surface facing the second interposer. External connection terminals are provided on a surface of the second interposer opposite to the surface on which the second semiconductor element is mounted. The first and second interposers are electrically connected to each other by conductive members provided therebetween. A back surface of the first semiconductor element and a back surface of the second semiconductor element are fixed to each other by an adhesive.

摘要翻译： 叠层型半导体器件具有降低的整体高度和提高层叠结构的机械强度的可靠性。 该半导体器件还具有改善的放热特性。 第一插入件具有其上形成有第一电极焊盘的表面，并且第一半导体元件安装有面向第一插入件的电路形成表面。 第二插入件具有其上形成有第二电极焊盘的表面，并且第二半导体元件安装有面向第二插入件的电路形成表面。 外部连接端子设置在与安装有第二半导体元件的表面相对的第二插入件的表面上。 第一和第二插入件通过设置在它们之间的导电构件彼此电连接。 第一半导体元件的背面和第二半导体元件的背面通过粘合剂彼此固定。

公开(公告)号：US06923965B2

公开(公告)日：2005-08-02

申请号：US10680670

申请日：2003-10-06

申请人： Akira Takashima ,  Mark E. Mummert ,  Mansour Mohamadzadeh

发明人： Akira Takashima ,  Mark E. Mummert ,  Mansour Mohamadzadeh

IPC分类号： G01N33/50 ,  A61K9/06 ,  A61K9/08 ,  A61K38/00 ,  A61K38/08 ,  A61K38/10 ,  A61K45/08 ,  A61P37/06 ,  A61P43/00 ,  C07K7/08 ,  C12N15/09 ,  G01N33/15 ,  G01N33/566 ,  A61K39/00

CPC分类号： A61K38/10 ,  A61K38/08

摘要： The present invention provides peptides with a specific affinity for glycosaminoglycan molecules. These peptides may have any number of functions, including but not limited to use as inhibitors of glycosaminoglycan-mediated processes, enhancers of glycosaminoglycan-mediated processes, and as molecular probes to identify the presence of a specific glycosaminoglycan. Peptides of the invention may be directed against any glycosaminoglycan, including hyaluronic acid, chondroitin sulfate A, chondroitin sulfate C, dermatan sulfate, heparin, keratan sulfate, keratosulfate, chitin, chitosan 1, and chitosan 2. These isolated peptides may have therapeutic uses in the treatment or prevention of diseases involving infection, inflammatory diseases, cancer, infections, etc. The peptides may also have other biological functions such as contraception.

摘要翻译： 本发明提供对糖胺聚糖分子具有特异亲和性的肽。 这些肽可以具有任何数量的功能，包括但不限于用作糖胺聚糖介导的过程的抑制剂，糖胺聚糖介导的过程的增强剂，以及用于鉴定特定的糖胺聚糖的存在的分子探针。 本发明的肽可以针对任何糖胺聚糖，包括透明质酸，硫酸软骨素A，硫酸软骨素C，硫酸皮肤素，肝素，硫酸角质素，角硫酸盐，壳多糖，壳聚糖1和壳聚糖2.这些分离的肽可以具有治疗用途 治疗或预防涉及感染，炎性疾病，癌症，感染等的疾病。肽还可具有其他生物学功能，例如避孕。