公开(公告)号：US11789079B2

公开(公告)日：2023-10-17

申请号：US17211030

申请日：2021-03-24

申请人： Rohde & Schwarz GmbH & Co. KG

发明人： Michael Feilen

IPC分类号： G01R31/00 ,  G01R31/319 ,  G01R31/3193

CPC分类号： G01R31/31926 ,  G01R31/31935

摘要： A measurement system is described. The measurement system includes a test-and-measurement (T&A) circuit and an error analysis circuit. The T&A circuit is configured to generate measurement data. The measurement data includes at least one of analysis data and configuration data. The analysis data is associated with an analysis of at least one input signal. The configuration data is associated with at least one of a physical measurement setup of the measurement system and measurement settings of the measurement system. The T&A circuit further is configured to generate a graphic representation of the measurement data. The error analysis circuit is configured to identify errors or anomalies associated with the measurement data based on the graphic representation. Further, a measurement method is described.

公开(公告)号：US11789064B1

公开(公告)日：2023-10-17

申请号：US17852181

申请日：2022-06-28

申请人： International Business Machines Corporation

发明人： Huimei Zhou ,  Liqiao Qin ,  Miaomiao Wang ,  Effendi Leobandung

IPC分类号： G01R31/28 ,  G01R31/26 ,  G01R31/319 ,  H03K3/03 ,  H01L21/66

CPC分类号： G01R31/2824 ,  G01R31/2607 ,  G01R31/31924 ,  H01L22/34 ,  H03K3/0315

摘要： A ring oscillator circuit design includes three or more inverter stages connected in series. Each inverter stage includes one or more inverter devices including a PMOS device and a coupled NMOS device. The PMOS device in each of odd alternating inverter devices of the three or more inverter stages having a source terminal receiving power from a power rail conductor, and a source terminal of the coupled NMOS device in each of first alternating inverter devices is grounded. An output of a last inverter device of a last stage of the three or more inverter stages is connected to an input of a first inverter stage. The method measures a first frequency of a first ring oscillator circuit and measures a second frequency of a second ring oscillator circuit design to determine either a BTI or HCI failure mechanism of the first ring oscillator circuit based on the measurements.

公开(公告)号：US20230314513A1

公开(公告)日：2023-10-05

申请号：US18192488

申请日：2023-03-29

申请人： LAPIS Technology Co., Ltd.

发明人： Hiroshi YAMASAKI

IPC分类号： G01R31/319 ,  G01R31/317

CPC分类号： G01R31/31915 ,  G01R31/31726 ,  G01R31/31713

摘要： An in-circuit emulator device includes a CPU that generates a first address signal by executing a program in synchronization with a first clock signal, a real-time capture circuit that generates a second address signal in synchronization with a second clock signal having a higher frequency than the first clock signal, and a selector circuit that supplies the second address signal to a storage device during a first period of one cycle of the first clock signal, and supplies the first address signal to the storage device during the remaining second period. The storage device reads data from a storage location of an address identified by the second address signal while the second address signal is supplied, and writes data from the CPU to a storage location of an address identified by the first address signal or reads data from said storage location while the first address signal is supplied.

公开(公告)号：US20230314512A1

公开(公告)日：2023-10-05

申请号：US18330222

申请日：2023-06-06

申请人： Advantest Test Solutions, Inc.

发明人： Karthik RANGANATHAN ,  Gregory CRUZAN ,  Samer Kabbani ,  Gilberto Oseguera ,  Ira Leventhal ,  Hiroki Ikeda ,  Toshiyuki Kiyokawa

IPC分类号： G01R31/319

CPC分类号： G01R31/31905 ,  G01R31/31907

摘要： A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

公开(公告)号：US11774498B2

公开(公告)日：2023-10-03

申请号：US17340631

申请日：2021-06-07

申请人： International Business Machines Corporation

发明人： David Wells Winston ,  Tong Li ,  Richard Daniel Kimmel

IPC分类号： G01R31/319 ,  G06N20/00 ,  G01R31/3183

CPC分类号： G01R31/31901 ,  G01R31/318314 ,  G01R31/318357 ,  G06N20/00

摘要： System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

公开(公告)号：US20230296672A1

公开(公告)日：2023-09-21

申请号：US18144848

申请日：2023-05-09

申请人： Ceremorphic, Inc.

发明人： Robert F. Wiser ,  Shakti SINGH ,  Neelam SURANA

IPC分类号： G01R31/3185 ,  H03K3/3562 ,  G01R31/319 ,  H03K3/0233 ,  G01R31/317 ,  H03K3/037

CPC分类号： G01R31/318583 ,  H03K3/35625 ,  G01R31/31924 ,  H03K3/02332 ,  G01R31/318572 ,  G01R31/318541 ,  G01R31/31723 ,  H03K3/0372

摘要： A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

公开(公告)号：US20230288476A1

公开(公告)日：2023-09-14

申请号：US17807283

申请日：2022-06-16

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Huan LU

IPC分类号： G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  G01R31/3183 ,  G01R31/3185

CPC分类号： G01R31/31711 ,  G01R31/31901 ,  G01R31/31937 ,  G01R31/31835 ,  G01R31/318569

摘要： Embodiments of the present disclosure relate to a method and an apparatus of analyzing data, and a storage medium. The method of analyzing data includes: obtaining a single shmoo plot of each pin of a memory particle; and constructing an integrated shmoo plot of the memory particle based on the single shmoo plot of each of the pins, wherein each test point of the integrated shmoo plot is marked with a pass proportion, and the pass proportion is configured to represent a proportion of a quantity of passed single shmoo plots at a corresponding test point to a total quantity of the single shmoo plots.

公开(公告)号：US11754624B1

公开(公告)日：2023-09-12

申请号：US17679686

申请日：2022-02-24

申请人： Seagate Technology LLC

发明人： Bharat Londhe ,  Deep Neema ,  Komal Shah

IPC分类号： G01R31/3177 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3181 ,  G01R31/319

CPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/31921 ,  G01R31/318307 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318547

摘要： A method includes injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test result representing the plurality of scan chains. The method also includes, in response to the compressed scan test result being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output. The debug circuit enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.

公开(公告)号：US20230258721A1

公开(公告)日：2023-08-17

申请号：US17671999

申请日：2022-02-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHANG HSIEN YANG ,  CHUNG-CHIEH YANG ,  YUNG-CHOW PENG ,  CHIH-CHIANG CHANG

IPC分类号： G01R31/319 ,  H03K3/037 ,  H03K5/26 ,  G01R31/317 ,  G01R31/3183

CPC分类号： G01R31/31922 ,  H03K3/037 ,  H03K5/26 ,  G01R31/31725 ,  G01R31/3191 ,  G01R31/318328

摘要： A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

公开(公告)号：US11714132B2

公开(公告)日：2023-08-01

申请号：US17219297

申请日：2021-03-31

申请人： Advantest Corporation

发明人： Mei-Mei Su ,  Seth Craighead

IPC分类号： G01R31/319 ,  G01R31/28

CPC分类号： G01R31/31908 ,  G01R31/2875 ,  G01R31/31905

摘要： Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances. In one exemplary implementation, the test equipment component is a test control component (e.g., a field programmable gate array (FPGA), etc.).