公开(公告)号：US11903192B2

公开(公告)日：2024-02-13

申请号：US17381599

申请日：2021-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Josh Lin ,  Chia-Ta Hsieh ,  Chen-Ming Huang ,  Chi-Wei Ho

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768 ,  H10B41/10 ,  H10B41/40 ,  H10B41/42 ,  H01L23/485

CPC classification number: H10B41/30 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76877 ,  H01L29/42324 ,  H01L29/6653 ,  H10B41/10 ,  H10B41/40 ,  H10B41/42 ,  H01L23/485 ,  H01L29/6656

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate structure over a substrate and laterally surrounded by a first sidewall spacer. The first gate structure protrudes outward from a top of the first sidewall spacer. A second gate structure is over the substrate and is laterally surrounded by a second sidewall spacer. The first gate structure has a first height that is larger than a second height of the second gate structure. The first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.

公开(公告)号：US11882697B2

公开(公告)日：2024-01-23

申请号：US17697380

申请日：2022-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shu Shimizu

IPC: H01L29/788 ,  H01L27/06 ,  H01L21/70 ,  H10B41/42 ,  H01L29/66

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883

Abstract: A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.

公开(公告)号：US11844213B2

公开(公告)日：2023-12-12

申请号：US17854068

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC: G11C16/00 ,  H10B41/35 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  G11C16/10 ,  H10B41/41 ,  H10B41/42 ,  G11C16/30

CPC classification number: H10B41/35 ,  G11C16/10 ,  H01L29/0649 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/41 ,  H10B41/42 ,  G11C16/30

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.

公开(公告)号：US11825651B2

公开(公告)日：2023-11-21

申请号：US17135744

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L29/423 ,  H10B41/42 ,  H10B41/35 ,  H01L21/28 ,  H10B41/30 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30 ,  H01L29/66

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US11765904B2

公开(公告)日：2023-09-19

申请号：US17942249

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Masaki Tsuji ,  Yoshiaki Fukuzumi

IPC: H01L27/11582 ,  H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

CPC classification number: H10B43/27 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

公开(公告)号：US20230209823A1

公开(公告)日：2023-06-29

申请号：US18178527

申请日：2023-03-05

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang

IPC: H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/40114 ,  H01L29/42328 ,  H10B41/30

Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

公开(公告)号：US20230189520A1

公开(公告)日：2023-06-15

申请号：US18103265

申请日：2023-01-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Guo Xiang Song ,  Chunming Wang ,  Leo Xing ,  Xian Liu ,  Nhan Do

IPC: H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7883 ,  H10B41/30

Abstract: A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.

公开(公告)号：US12219766B2

公开(公告)日：2025-02-04

申请号：US18446579

申请日：2023-08-09

Applicant: Kioxia Corporation

Inventor： Masaki Tsuji ,  Yoshiaki Fukuzumi

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

公开(公告)号：US12200926B2

公开(公告)日：2025-01-14

申请号：US17949962

申请日：2022-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.

公开(公告)号：US12166011B1

公开(公告)日：2024-12-10

申请号：US17230890

申请日：2021-04-14

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Debo Olaosebikan

IPC: G11C11/401 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B41/42 ,  G11C5/06 ,  G11C11/54

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.