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60 条记录 (耗时 0.026 秒)

    Phase deglitch circuit for phase interpolator for high-speed serial I/O applications
    21.
    发明授权
    Phase deglitch circuit for phase interpolator for high-speed serial I/O applications 有权
    用于高速串行I / O应用的相位内插器的相位去离子电路

    公开(公告)号：US07653167B2

    公开(公告)日：2010-01-26

    申请号：US11517162

    申请日：2006-09-07

    申请人： Hongjiang Song ,  Tofayel Ahmed

    发明人： Hongjiang Song ,  Tofayel Ahmed

    IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

    CPC分类号： H04L7/002 ,  H03L7/0812 ,  H03L7/091

    摘要： Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

    摘要翻译： 各种实施例提供接收输入时钟并输出符号间干扰均衡的相移输出时钟的相位插值器（PI）。 在一个实施例中，相位插值器包括两个PI调节器和PI混合器。 在一个实施例中，PI调节器接收输入时钟，并且通过使用诸如触发器的合适电路元件由不同的相移输入时钟控制。 总而言之，输入时钟控制PI调节器和混频器协调一致地控制PI调节器的频带限制效应，这进而使码间干扰相等。

    DATA RECEPTION APPARATUS AND DATA COMMUNICATION SYSTEM
    26.
    发明申请
    DATA RECEPTION APPARATUS AND DATA COMMUNICATION SYSTEM 有权
    数据接收装置和数据通信系统

    公开(公告)号：US20150063514A1

    公开(公告)日：2015-03-05

    申请号：US14537969

    申请日：2014-11-11

    申请人： DENSO CORPORATION

    发明人： Hironobu AKITA ,  Nobuaki MATSUDAIRA ,  Hirofumi YAMAMOTO

    IPC分类号： H04L7/00 ,  H04L7/033 ,  G11C27/02

    CPC分类号： H04L7/0087 ,  G11C27/02 ,  H04L7/002 ,  H04L7/0025 ,  H04L7/0331 ,  H04L7/0337 ,  H04L7/0338 ,  H04L7/046

    摘要： A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples).

    摘要翻译： 数据接收装置通过对比特串的比特数进行积分来获得积分的比特数，通过对通过对每个比特进行过采样而获得的样本数的积分来获得积分的样本数，获得表示积分数 的比特和积分的样本数量，基于近似线，确定对应于在综合采样数之后的过采样数据中相同值继续的段的比特串的比特长度。 即使当接收侧时钟源对发送侧时钟源具有一定程度的时钟频率误差时，也可以以高于过采样周期（数字的倒数）的精度获得比特串对应的一位的多少个样本 的样品）。

    Information processing apparatus, synchronization correction method and computer program
    27.
    发明授权
    Information processing apparatus, synchronization correction method and computer program 有权
    信息处理装置，同步校正方法和计算机程序

    公开(公告)号：US08971355B2

    公开(公告)日：2015-03-03

    申请号：US12793039

    申请日：2010-06-03

    申请人： Seiji Ohbi

    发明人： Seiji Ohbi

    IPC分类号： H04N21/43 ,  H04N5/765 ,  H04N21/2343 ,  H04N21/436

    CPC分类号： H04L7/002 ,  H04L67/42 ,  H04N5/765 ,  H04N21/234318 ,  H04N21/4302 ,  H04N21/4307 ,  H04N21/43615

    摘要： An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time.

    摘要翻译： 提供了一种信息处理装置，其包括：发送单元，用于发送用于查询另一设备的查询请求，以获得由其他设备保存的计数值;接收单元，用于从该另一设备接收计数值的返回;校正单元， 基于所接收的计数值，在预定的时间段执行用于使采样频率与这种其他设备同步的校正处理，以及用于基于采样频率与这种其他设备同步再现内容的再现单元。 校正单元通过考虑在查询请求的发送和返回的接收之间的往返时间以及在先前校正时间发生的残差而进行校正。

    Method and System for Providing Data Communication in Continuous Glucose Monitoring and Management System
    28.
    发明申请
    Method and System for Providing Data Communication in Continuous Glucose Monitoring and Management System 审中-公开
    在连续葡萄糖监测管理系统中提供数据通信的方法和系统

    公开(公告)号：US20140323960A1

    公开(公告)日：2014-10-30

    申请号：US14325253

    申请日：2014-07-07

    申请人： Abbott Diabetes Care Inc.

    发明人： Mark Kent Sloan

    IPC分类号： A61M5/172 ,  H04B7/24

    CPC分类号： A61M5/1723 ,  A61B5/0002 ,  A61B5/01 ,  A61B5/14532 ,  A61M2205/3592 ,  G06F19/3418 ,  G16H40/67 ,  H04B7/24 ,  H04L7/002 ,  H04L7/0079 ,  H04L7/0091

    摘要： Method and system for providing data monitoring and management including RF communication link over which a transmitter and a receiver is configured to communicate, the transmitter configured to periodically transmit a data packet associated with a detected analyte level received from an analyte sensor, and the receiver configured to identify the transmitter as the correct transmitter for which it is configured to receive the data packets, and to continue to receive the data packets from the transmitter once the transmitter identification has been verified, is provided.

    摘要翻译： 用于提供数据监视和管理的方法和系统，包括RF通信链路，发射器和接收器在该通信链路上被配置为通信，所述发射机被配置为周期性地发送与从分析物传感器接收的检测到的分析物水平相关联的数据分组， 将发射机识别为其被配置为接收数据分组的正确发射机，并且在发送器标识被验证之后继续接收来自发射机的数据分组。

    Apparatus and methods for invertible sine-shaping for phase interpolation
    29.
    发明授权
    Apparatus and methods for invertible sine-shaping for phase interpolation 有权
    用于相位插值的可逆正弦整形的装置和方法

    公开(公告)号：US08754678B1

    公开(公告)日：2014-06-17

    申请号：US13835598

    申请日：2013-03-15

    申请人： Analog Devices, Inc.

    发明人： Robert Schell

    IPC分类号： H03B28/00 ,  H03B25/00 ,  H04L7/033 ,  H04L7/06

    CPC分类号： H03K3/012 ,  H03B28/00 ,  H03K4/92 ,  H04L7/002

    摘要： Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.

    摘要翻译： 提供了正交时钟信号生成的装置和方法。 在某些实现中，一种装置包括被配置为接收同相时钟信号，正交相位时钟信号和反相控制信号的可逆正弦整形滤波器。 可逆正弦整形滤波器还被配置为对同相和正交相位时钟信号进行滤波以产生正弦同相和正交相位时钟信号。 可逆正弦整形滤波器还被配置为基于反相控制信号选择性地反相同相和正交相位时钟信号中的一个或两者。 该装置还包括相位插值器，其被配置为基于选择性反转的正弦同相时钟信号和正交相位正弦时钟信号的加权和产生内插时钟信号。 同相时钟信号和正交相位时钟信号具有正交相位关系。

    Low power clock and data recovery phase interpolator
    30.
    发明授权
    Low power clock and data recovery phase interpolator 有权
    低功耗时钟和数据恢复相位插值器

    公开(公告)号：US08063683B2

    公开(公告)日：2011-11-22

    申请号：US12480604

    申请日：2009-06-08

    申请人： Hui Wang ,  Lixin Jiang ,  Yehui Sun

    发明人： Hui Wang ,  Lixin Jiang ,  Yehui Sun

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0807 ,  H03L7/0814 ,  H04L7/002

    摘要： A phase interpolator is provided. The phase interpolator comprises a plurality of reference stages, the reference stages receiving a reference signal having a predetermined phase and outputting a component signal, wherein the reference stages comprise a plurality of current source circuits, and the current source circuits comprise a plurality of transistors, and the transistors of the current source circuits are coupled to one another by the drains of the transistors.

    摘要翻译： 提供了相位插值器。 相位插值器包括多个参考级，参考级接收具有预定相位的参考信号并输出​​分量信号，其中参考级包括多个电流源电路，并且电流源电路包括多个晶体管， 并且电流源电路的晶体管通过晶体管的漏极彼此耦合。