公开(公告)号：US08603911B2

公开(公告)日：2013-12-10

申请号：US13105338

申请日：2011-05-11

Applicant: Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

Inventor： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

IPC: H01L21/44 ,  H01L23/12 ,  H01L29/40

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

Abstract translation: 半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。 该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成， 另一个。 每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。 缓冲层设置在积聚结构上。 通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。

公开(公告)号：US20120083076A1

公开(公告)日：2012-04-05

申请号：US13324592

申请日：2011-12-13

Applicant: Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

Inventor： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

Abstract: A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

Abstract translation: MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。 栅极电介质突出超过栅电极。 在栅极的任一侧形成具有浅延伸的深源极和漏极。 深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。 延伸部位于与栅极电介质接触的栅极下方。 选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。 描述制造MOSFET的方法。

公开(公告)号：US08054149B2

公开(公告)日：2011-11-08

申请号：US11822230

申请日：2007-07-03

Applicant: Mean-Jue Tung ,  Wen-Song Ko ,  Yu-Ting Huang ,  Yen-Ping Wang

Inventor： Mean-Jue Tung ,  Wen-Song Ko ,  Yu-Ting Huang ,  Yen-Ping Wang

IPC: H01F27/02 ,  H01F27/36 ,  H01F38/12 ,  H01F21/00 ,  H01F5/00

CPC classification number: H01F17/04 ,  H01F27/255 ,  H01F27/34 ,  H01F41/0246 ,  H01F2003/103 ,  H01F2017/046

Abstract: This invention discloses a monolithic inductor including a body made by compressing a magnetic powder, a coil positioned in the body, and a permanent magnet positioned in the body and in a magnetic circuit formed by applying current to the coil. The monolithic inductor of this invention includes the magnetic body containing the permanent magnet and the coil. The permanent magnet in the magnetic circuit (path of magnetic flux lines) formed by applying current to the coil generates a reverse-bias magnetic field, thereby increasing the operating range of the magnetic body, the saturation current of the magnetic body, and the rated current of the inductor.

Abstract translation: 本发明公开了一种单片电感器，其包括通过压缩磁粉制成的主体，位于本体中的线圈和位于本体中的永磁体以及通过向线圈施加电流而形成的磁路。 本发明的单片电感器包括包含永磁体和线圈的磁体。 通过向线圈施加电流而形成的磁路（磁通线路径）中的永磁体产生反向偏置磁场，从而增加磁体的工作范围，磁体的饱和电流和额定值 电感电流。

公开(公告)号：US07719325B1

公开(公告)日：2010-05-18

申请号：US12273011

申请日：2008-11-18

Applicant: Yen-Ping Wang ,  Yen-Hui Wang ,  Pei-Yuan Chen

Inventor： Yen-Ping Wang ,  Yen-Hui Wang ,  Pei-Yuan Chen

IPC: H03B1/00

CPC classification number: H03K5/1252 ,  H03K17/162

Abstract: An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.

Abstract translation: 用于共模干扰消除的有源负载主导电路，其在第一电压电势和第二电压电位之间被偏置，并具有伴随的共模故障干扰源。 有源负载主导电路包括一对上拉网络和一对有源负载网络。 由于一对上拉网络的对称结构，共模干扰信号被抵消。 至少一个设置信号和至少一个复位信号响应于时钟信号或补码时钟信号提供给锁存器。 设定信号和复位信号中的至少一个可以被上拉至第一电压电位或下拉至第二电压电位。 设定信号和复位信号的电压差对于锁存器来说足够大。

公开(公告)号：US07615426B2

公开(公告)日：2009-11-10

申请号：US11118730

申请日：2005-04-29

Applicant: Chih-Hao Wang ,  Yen-Ping Wang ,  Pang-Yen Tsai

Inventor： Chih-Hao Wang ,  Yen-Ping Wang ,  Pang-Yen Tsai

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/76 ,  H01L29/94 ,  H01L27/01

CPC classification number: H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849

Abstract: A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact etch stop layer on said gate and said spacers, and said source and drain. The contact etch stop layer is substantially locally continuous in a direction perpendicular to the channel region length and substantially locally discontinuous in a direction parallel to the channel region length.

Abstract translation: 一种具有不连续接触蚀刻停止层的晶体管，包括：具有表面的衬底，所述衬底的所述表面上的栅极电介质，所述栅极电介质上的栅极电极，沿着所述栅极电介质和栅电极的侧壁的间隔物，源极 以及分别在所述栅极电介质和所述栅电极的相对侧上形成的漏极，所述源极和漏极限定了沟道区，所述沟道区具有基本上从所述源延伸到所述漏极的沟道长度，以及在其间的衬底中的接触蚀刻停止 所述栅极和所述间隔物上的层，以及所述源极和漏极。 接触蚀刻停止层在垂直于沟道区长度的方向上基本上局部连续，并且在平行于沟道区长度的方向上基本上局部不连续。

公开(公告)号：US07429907B2

公开(公告)日：2008-09-30

申请号：US11553936

申请日：2006-10-27

Applicant: Mean-Jue Tung ,  Wen-Song Ko ,  Yu-Ting Huang ,  Ping-Feng Hsu ,  Yen-Ping Wang

Inventor： Mean-Jue Tung ,  Wen-Song Ko ,  Yu-Ting Huang ,  Ping-Feng Hsu ,  Yen-Ping Wang

IPC: H01F27/08

CPC classification number: H01F27/22 ,  H01F27/255 ,  H01F37/00

Abstract: The present invention relates to a power inductor having a heat dissipating structure formed on the surface thereof, which comprises: at least a conducting wire; and a cladding, made of a magnetic material for wrapping the conductive wire, having the heat dissipating structure of embossed patterns formed on the surface thereof. Preferably, the embossed pattern can be a cone, a cuboid, a column, or the combination thereof. Moreover, the length of any edge or the diameter of any one of the embossed patterns is about 1%˜50% of that of the power inductor, and the height of any one of the embossed patterns is about 1%˜50% of the thickness of the power inductor.

Abstract translation: 本发明涉及一种在其表面上形成有散热结构的功率电感器，其包括：至少导电线; 以及由用于缠绕导电线的磁性材料制成的包层，其具有形成在其表面上的压花图案的散热结构。 优选地，压纹图案可以是锥体，长方体，柱或其组合。 此外，任何一个压花图案的任何一个边缘或直径的长度为功率电感器的长度的约1％〜50％，并且任何一个压纹图案的高度为约1％〜50％ 功率电感的厚度。

公开(公告)号：US20070093033A1

公开(公告)日：2007-04-26

申请号：US11258469

申请日：2005-10-24

Applicant: Chih-Hao Wang ,  Yen-Ping Wang ,  Steve Ting ,  Yi-Chun Huang

Inventor： Chih-Hao Wang ,  Yen-Ping Wang ,  Steve Ting ,  Yi-Chun Huang

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.

Abstract translation: 提供了一种超浅结（USJ）FET器件及其形成方法，其具有改善的对SDE或LDD掺杂区界面的控制以提高器件性能和可靠性，该方法包括提供半导体衬底; 形成栅极结构，所述栅极结构包括栅极电介质，上覆栅极电极和邻近所述栅电极的任一侧的第一偏移间隔物; 在与相应的第一偏移间隔物相邻的相应源极和漏极区域上形成包含掺杂剂的至少一个掺杂半导体层; 在相邻的第一偏移间隔物附近形成第二偏移间隔物; 并且对所述至少一个半导体层进行热处理以引起所述掺杂剂的扩散以在所述半导体衬底中形成掺杂区域。

公开(公告)号：US20050250271A1

公开(公告)日：2005-11-10

申请号：US10839430

申请日：2004-05-05

Applicant: Chih-Hao Wang ,  Tzung-Lin Li ,  Yen-Ping Wang ,  Chun-Yen Chang

Inventor： Chih-Hao Wang ,  Tzung-Lin Li ,  Yen-Ping Wang ,  Chun-Yen Chang

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823842

Abstract: Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over at least a portion of the second region. The metal layer is heated to form a metal gate electrode over the first region, and the metal layer and the semiconductor layer are collectively heated to form a composite metal gate electrode over the second region.

Abstract translation: 在一个实施例中，制造晶体管栅极的方法包括在衬底的第一和第二区域上形成金属层，其中第一和第二区域分别具有不同的第一和第二掺杂剂类型。 在第二区域的至少一部分上形成半导体层。 金属层被加热以在第一区域上形成金属栅电极，并且金属层和半导体层被共同加热，以在第二区域上形成复合金属栅电极。

公开(公告)号：US08304665B2

公开(公告)日：2012-11-06

申请号：US12266674

申请日：2008-11-07

Applicant: Chiang-Cheng Chang ,  Yen-Ping Wang ,  Don-Son Jiang ,  Jeng-Yuan Lai ,  Yu-Po Wang

Inventor： Chiang-Cheng Chang ,  Yen-Ping Wang ,  Don-Son Jiang ,  Jeng-Yuan Lai ,  Yu-Po Wang

IPC: H05K1/11 ,  H05K1/09 ,  H01R9/00

CPC classification number: H05K1/116 ,  H05K1/114 ,  H05K2201/09545 ,  H05K2201/09563

Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.

Abstract translation: 提出了具有无地导电迹线的封装衬底，其包括形成在其中的多个电镀通孔的芯层和形成在芯层的至少表面上的多个导电迹线。 每个导电迹线具有连接端，接合焊盘端和连接连接端和接合焊盘端的基体，导电迹线通过连接端电连接到相应的一个电镀通孔，以及 连接端具有大于基体的宽度，但不大于电镀通孔的直径，从而增加导电迹线和电镀通孔之间的接触面积，并且防止导电迹线的接触表面与 电镀通孔破裂。

公开(公告)号：US07727845B2

公开(公告)日：2010-06-01

申请号：US11258469

申请日：2005-10-24

Applicant: Chih-Hao Wang ,  Yen-Ping Wang ,  Steve Ming Ting ,  Yi-Chun Huang

Inventor： Chih-Hao Wang ,  Yen-Ping Wang ,  Steve Ming Ting ,  Yi-Chun Huang

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/20

CPC classification number: H01L29/6659 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.

Abstract translation: 提供了一种超浅结（USJ）FET器件及其形成方法，其具有改善的对SDE或LDD掺杂区界面的控制以提高器件性能和可靠性，该方法包括提供半导体衬底; 形成栅极结构，所述栅极结构包括栅极电介质，上覆栅极电极和邻近所述栅电极的任一侧的第一偏移间隔物; 在与相应的第一偏移间隔物相邻的相应源极和漏极区域上形成包含掺杂剂的至少一个掺杂半导体层; 在相邻的第一偏移间隔物附近形成第二偏移间隔物; 并且对所述至少一个半导体层进行热处理以引起所述掺杂剂的扩散以在所述半导体衬底中形成掺杂区域。