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    Epitaxial channel with a counter-halo implant to improve analog gain
    21.
    发明授权
    Epitaxial channel with a counter-halo implant to improve analog gain 有权
    具有反向晕轮植入的外延通道，以改善模拟增益

    公开(公告)号：US09425099B2

    公开(公告)日：2016-08-23

    申请号：US14156496

    申请日：2014-01-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

    CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

    Abstract: Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors.

    Abstract translation: 本公开的一些实施例涉及一种改善长沟道晶体管性能的植入物，对短沟道晶体管性能几乎没有影响。 为了减轻DIBL，衬底上的长沟道晶体管和短沟道晶体管都经历晕圈植入。 虽然光晕植入改善了短沟道晶体管的性能，但是它会降低长沟道晶体管的性能。 因此，仅在长沟道晶体管上执行反向注入才能恢复其性能。 为了实现这一点，反向注入以在长沟道晶体管的源极/漏极区附近引入掺杂剂杂质以抵消晕轮植入物的影响的角度进行，而反向晕轮植入物同时被遮蔽而达到 短沟道晶体管的通道。

    Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices
    22.
    发明申请
    Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices 有权
    位错应力记忆技术（DSMT）在外延通道器件上的应用

    公开(公告)号：US20150295085A1

    公开(公告)日：2015-10-15

    申请号：US14252147

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

    IPC: H01L29/78 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

    Abstract translation: 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向外延沟道区域提供应力的位错应力存储（DSM）区域和相关联的形成方法。 晶体管器件具有设置在半导体衬底上的外延层，以及设置在外延层上的栅极结构。 沟道区域在位于栅极结构的相对侧的外延源极和漏极区域之间的栅极结构的下方延伸。 第一和第二位错应力记忆（DSM）区域具有在沟道区域内产生应力的应力晶格。 第一和第二DSM区域分别从外延源区域的下面延伸到外延源区域内的从外延漏极区域下方的第一位置到外延漏极区域内的第二位置。 使用第一和第二DSM区域来压缩通道区域，提高了设备​​性能。

    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN
    23.
    发明申请
    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN 有权
    外来通道与计数器植入物提高模拟增益

    公开(公告)号：US20150200139A1

    公开(公告)日：2015-07-16

    申请号：US14156496

    申请日：2014-01-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

    IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L29/16

    CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

    Abstract: Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors.

    Abstract translation: 本公开的一些实施例涉及一种改善长沟道晶体管性能的植入物，对短沟道晶体管性能几乎没有影响。 为了减轻DIBL，衬底上的长沟道晶体管和短沟道晶体管都经历晕圈植入。 虽然光晕植入改善了短沟道晶体管的性能，但是它会降低长沟道晶体管的性能。 因此，仅在长沟道晶体管上执行反向注入才能恢复其性能。 为了实现这一点，反向注入以在长沟道晶体管的源极/漏极区附近引入掺杂剂杂质以抵消晕轮植入物的影响的角度进行，而反向晕轮植入物同时被遮蔽而达到 短沟道晶体管的通道。

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