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21.发明授权公开(公告)号：US08732628B1
公开(公告)日：2014-05-20
申请号：US13742689
申请日：2013-01-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Meng-Fan Wu , I-Fan Lin , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
IPC: G06F17/50
CPC classification number: G03F1/70 , G03F1/38 , G03F7/70466
Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.
Abstract translation: 一种方法包括：在使用双重图案化技术（DPT）制造的集成电路（IC）的布局中选择电路图案的电路图案或网络。 所选择的电路图案或网络附近的电路图案被分组成一个或多个组。 对于每个组，对于两组不同的掩模分配，计算与掩模对准误差相关联的相应的预期电阻 - 电容（RC）提取误差成本。 一个或多个组中的电路图案被分配为通过相应的光掩模进行图案化，以便最小化预期RC提取误差成本的总和。
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公开(公告)号：US08707230B1
公开(公告)日：2014-04-22
申请号：US13792827
申请日：2013-03-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Yi Hu , Chin-Cheng Kuo , Cheng-Hung Yeh , Jui-Feng Kuan , Yi-Kan Cheng
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5036 , G06F2217/10
Abstract: An integrated circuit (IC) simulation method comprises providing a device process model from a non-transitory machine readable storage medium into a programmed computer. The device process model includes one or more device variables. Each device variable defines a probability distribution of an active-device-level variation of devices in an IC. A conductive line model and/or a multi patterning technology (MPT) model is provided from the storage medium to the computer. The conductive line model includes one or more conductive line variables. Each conductive line variable defines a probability distribution of a conductive-line process-induced variation. The MPT model includes one or more MPT variables. Each MPT variable defines a probability distribution of a mask-misalignment-induced conductive line coupling variation. A Monte Carlo simulation is performed in the computer, including the device process model and the conductive line model or MPT model, to identify parasitic couplings in the IC.
Abstract translation: 集成电路（IC）模拟方法包括将设备处理模型从非暂时机器可读存储介质提供到编程计算机中。 设备过程模型包括一个或多个设备变量。 每个器件变量定义IC中器件的有源器件级变化的概率分布。 从存储介质向计算机提供导线模型和/或多图案形成技术（MPT）模型。 导线模型包括一个或多个导线变量。 每个导线变量定义了导线处理引起的变化的概率分布。 MPT模型包括一个或多个MPT变量。 每个MPT变量定义了掩模 - 未对准引起的导线耦合变化的概率分布。 在计算机中执行蒙特卡罗模拟，包括器件工艺模型和导线模型或MPT模型，以识别IC中的寄生耦合。
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公开(公告)号：US20140013292A1
公开(公告)日：2014-01-09
申请号：US13723248
申请日：2012-12-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wen-Hao CHEN , Yi-Kan Cheng
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5031 , G06F17/504 , G06F2217/84
Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.
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公开(公告)号：US12223252B2
公开(公告)日：2025-02-11
申请号：US18171072
申请日：2023-02-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fong-yuan Chang , Chin-Chou Liu , Chin-Her Chien , Cheng-Hung Yeh , Po-Hsiang Huang , Sen-Bor Jan , Yi-Kan Cheng , Hsiu-Chuan Shu
IPC: G06F30/394 , G06F30/392 , G06F30/398
Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
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公开(公告)号：US20240105619A1
公开(公告)日：2024-03-28
申请号：US18523553
申请日：2023-11-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fong-Yuan Chang , Noor Mohamed Ettuveettil , Po-Hsiang Huang , Sen-Bor Jan , Ming-Fa Chen , Chin-Chou Liu , Yi-Kan Cheng
IPC: H01L23/528 , H01L23/00 , H01L23/522
CPC classification number: H01L23/5286 , H01L23/5226 , H01L24/09 , H01L2224/08135 , H01L2224/08137 , H01L2224/08145 , H01L2224/08146 , H01L2224/08147
Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
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Patent Agency Ranking
公开(公告)号：US11532613B2
公开(公告)日：2022-12-20
申请号：US17163960
申请日：2021-02-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hui-Yu Lee , Chi-Wen Chang , Jui-Feng Kuan , Yi-Kan Cheng
Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
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公开(公告)号：US20220336356A1
公开(公告)日：2022-10-20
申请号：US17854683
申请日：2022-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fong-Yuan Chang , Noor Mohamed Ettuveettil , Po-Hsiang Huang , Sen-Bor Jan , Ming-Fa Chen , Chin-Chou Liu , Yi-Kan Cheng
IPC: H01L23/528 , H01L23/522 , H01L23/00
Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
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公开(公告)号：US11088084B2
公开(公告)日：2021-08-10
申请号：US16863934
申请日：2020-04-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hui Yu Lee , Chin-Chou Liu , Cheng-Hung Yeh , Fong-Yuan Chang , Po-Hsiang Huang , Yi-Kan Cheng , Ka Fai Chang
IPC: H01L23/552 , H01L49/02 , H01L23/498 , H01L23/522 , G06F30/392 , G06F30/394 , G06F30/398 , H01L27/02
Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.
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公开(公告)号：US20210159225A1
公开(公告)日：2021-05-27
申请号：US17163960
申请日：2021-02-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hui-Yu Lee , Chi-Wen Chang , Jui-Feng Kuan , Yi-Kan Cheng
Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
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公开(公告)号：US20170186691A1
公开(公告)日：2017-06-29
申请号：US15361970
申请日：2016-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kuo-Nan Yang , Chung-Hsing Wang , Yi-Kan Cheng , Kumar Lalgudi
IPC: H01L23/528 , G06F17/50 , H03K5/15
CPC classification number: G06F17/5077 , G06F17/5081 , G06F2217/62 , H01L23/528 , H01L23/5283 , H01L23/5286 , H03K5/15066
Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.
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