公开(公告)号：US12205886B2

公开(公告)日：2025-01-21

申请号：US17873590

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088

Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.

公开(公告)号：US12113021B2

公开(公告)日：2024-10-08

申请号：US18357286

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53276 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.

公开(公告)号：US11848190B2

公开(公告)日：2023-12-19

申请号：US17984443

申请日：2022-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Min Cao ,  Ming-Han Lee ,  Shau-Lin Shue ,  Shin-Yi Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L21/76846 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L21/3212

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US20230387018A1

公开(公告)日：2023-11-30

申请号：US18359383

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53276 ,  H01L21/76802 ,  H01L21/76871 ,  H01L21/76864 ,  H01L21/76846 ,  H01L23/5283 ,  H01L23/5226 ,  H01L21/76877 ,  H01L21/3212

Abstract: A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

公开(公告)号：US20230386910A1

公开(公告)日：2023-11-30

申请号：US18359486

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76805 ,  H01L21/76843 ,  H01L23/535 ,  H01L23/53209 ,  H01L21/76832 ,  H01L23/53238 ,  H01L23/53252 ,  H01L21/76895 ,  H01L21/76841 ,  H01L21/76829 ,  H01L23/53223

Abstract: A semiconductor structure includes a contact over a substrate, an interlayer dielectric (ILD) layer including a first region disposed directly above the contact and a second region disposed adjacent to the first region, first conductive features embedded in the first region and separated by a first distance, a dielectric layer embedded in the ILD layer and disposed between the first conductive features in the first region, and second conductive features disposed in the second region and separated by a second distance greater than the first distance. The second region is free of the dielectric layer.

公开(公告)号：US20230369114A1

公开(公告)日：2023-11-16

申请号：US18359070

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Chia-Tien Wu ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L21/76829 ,  H01L21/76886 ,  H01L29/45 ,  H01L21/76837 ,  H01L21/7684 ,  H01L23/528

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

公开(公告)号：US11538749B2

公开(公告)日：2022-12-27

申请号：US17097505

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Cheng-Chin Lee ,  Kuang-Wei Yang ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.

公开(公告)号：US20220350262A1

公开(公告)日：2022-11-03

申请号：US17868398

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US11482447B2

公开(公告)日：2022-10-25

申请号：US16923424

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11422475B2

公开(公告)日：2022-08-23

申请号：US16722621

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.