公开(公告)号：US09679643B1

公开(公告)日：2017-06-13

申请号：US15065787

申请日：2016-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Cheng Chou

IPC: G11C11/00 ,  G11C11/36 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C8/00 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79 ,  G11C2213/82

Abstract: A device is disclosed that includes a driver, a sinker, a memory column, a reference column, a reference resistor and a sensing unit. At least one of the driver and the sinker has a trimmable resistance. For write operation, one of resistive memory cells is conducted based on a row location in the memory column thereof, the driver provides a write current flowing therethrough and the trimmable resistance is trimmed based on the row location. For read operation, the sensing unit senses a read current of the memory column and a reference current of the reference column and the reference resistor when one of the resistive memory cells and a positionally corresponding one of the reference bit cells are conducted.

公开(公告)号：US09625186B2

公开(公告)日：2017-04-18

申请号：US14013125

申请日：2013-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Cheng Chou ,  Po-Hao Lee ,  Jonathan Tehan Chen

IPC: F25B21/02 ,  H01L23/38

CPC classification number: H01L25/0657 ,  F25B21/02 ,  F25B2321/0212 ,  H01L23/38 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.

公开(公告)号：US09576653B1

公开(公告)日：2017-02-21

申请号：US15150478

申请日：2016-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Cheng Chou

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C13/0026 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.

Abstract translation: 电阻性存储单元的位线包括具有预定值的参考电阻器的参考分支和包括具有可变值的可调节存储器电阻器的单元分支。 参考分支基于参考电阻器的预定值产生参考电流，并且单元分支基于可调节存储电阻器的选定值产生单元分支电流。 读出放大器具有耦合到参考分支的第一输入和耦合到单元分支的第二输入。 第一预充电晶体管耦合到第一预充电电压和电池分支。 第一预充电晶体管被配置为在读取操作之前将单元分支预充电到第一预充电电压。

公开(公告)号：US09281031B2

公开(公告)日：2016-03-08

申请号：US14603393

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung Chang ,  Cheng Hung Lee ,  Chung-Cheng Chou ,  Hung-Jen Liao ,  Bin-Hau Lo

IPC: G11C17/00 ,  G11C7/12 ,  G11C7/06 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

公开(公告)号：US20150206583A1

公开(公告)日：2015-07-23

申请号：US14161193

申请日：2014-01-22

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chung-Cheng Chou ,  Yue-Der Chih

IPC: G11C13/00 ,  H03K17/56

CPC classification number: G11C13/0064 ,  G11C11/56 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2213/79 ,  H03K17/56

Abstract: A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source.

Abstract translation: 公开了一种包括电流源和电流比较器的电路。 电流源连接到电阻存储器单元以产生驱动电流。 电流比较器具有连接到电流源和电阻存储器单元的感测节点，以感测通过感测节点注入到电流比较器的注入电流，其中当电阻性存储器单元的电阻状态切换使得电流比较器确定 注入电流的量增加到超过或者减小到达阈值时，电流比较器关闭电流源。