公开(公告)号：US09934154B2

公开(公告)日：2018-04-03

申请号：US15174986

申请日：2016-06-06

申请人： Samsung Electronics Co., Ltd.

发明人： Krishna Malladi ,  Uksong Kang ,  Hongzhong Zheng

IPC分类号： G11C7/00 ,  G11C5/00 ,  G06F12/0897 ,  G06F13/16

CPC分类号： G06F12/0897 ,  G06F12/0811 ,  G06F12/0868 ,  G06F13/1673 ,  G06F2212/1016 ,  G06F2212/60

摘要： An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

公开(公告)号：US20170168931A1

公开(公告)日：2017-06-15

申请号：US15354354

申请日：2016-11-17

申请人： Samsung Electronics Co., Ltd.

发明人： Chankyung Kim ,  Uksong Kang ,  Sanguhn Cha ,  Sungyong Seo ,  Youngjin Cho ,  Seongil O

IPC分类号： G06F12/02 ,  G11C14/00 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

CPC分类号： G06F12/0871 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0853 ,  G06F12/0868 ,  G06F12/0895 ,  G06F2212/1004 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/313 ,  G06F2212/60 ,  G06F2212/601 ,  G06F2212/7203 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/005 ,  G11C11/4093 ,  G11C16/0483

摘要： A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.

公开(公告)号：US09305616B2

公开(公告)日：2016-04-05

申请号：US13943790

申请日：2013-07-17

申请人： Samsung Electronics Co., Ltd.

发明人： Haksoo Yu ,  Dae-Hyun Kim ,  Uksong Kang ,  Chulwoo Park ,  Joosun Choi ,  Hyojin Choi

IPC分类号： G06F12/00 ,  G11C7/10 ,  G06F12/02 ,  G06F12/06 ,  G11C11/403 ,  G11C11/406 ,  G11C29/00 ,  G11C29/44

CPC分类号： G11C7/1072 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0638 ,  G11C11/005 ,  G11C11/403 ,  G11C11/40622 ,  G11C29/783 ,  G11C2029/4402

摘要： A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.

摘要翻译： 提供一种半导体存储单元阵列，其包括第一存储单元阵列区域，该第一存储单元阵列区域包括布置在具有第一运行速度的矩阵中的芯片中的第一组存储单元; 以及第二存储单元阵列区域，包括布置在所述芯片中的行和列的矩阵并具有与所述第一操作速度不同的第二操作速度的第二组存储单元。 通过DRAM控制器的寻址来访问第一和第二存储单元阵列区域。