公开(公告)号：US09348679B2

公开(公告)日：2016-05-24

申请号：US14465105

申请日：2014-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hee Yoo ,  Sung Hyun Lee ,  Dongsoo Kang ,  Sua Kim ,  Haksoo Yu ,  Jaeyoun Youn ,  Hyojin Choi

IPC: G06F11/10 ,  G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/44

CPC classification number: G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/78 ,  G11C2029/4402

Abstract: A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

Abstract translation: 提供了不良页面管理系统以保证诸如DRAM之类的易失性半导体存储器件的产量。 DRAM中存在不良页面列表。 存储器控制器中的页面重新映射器与调度单元的正常操作并行执行页面重映射操作，以执行延迟开销隐藏功能。 DRAM的芯片尺寸减小或最小化。 DRAM控制器执行延迟开销隐藏功能来控制DRAM。

公开(公告)号：US09292425B2

公开(公告)日：2016-03-22

申请号：US13966585

申请日：2013-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Choi ,  Chulwoo Park ,  Uksong Kang ,  Haksoo Yu

IPC: G06F12/00 ,  G11C7/10 ,  G11C11/4076

CPC classification number: G06F12/00 ,  G11C7/1006 ,  G11C11/4076

Abstract: A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

Abstract translation: 半导体存储器件执行修改的读取操作或修改的写入操作。 半导体存储器件包括存储单元阵列，读取电路和写入电路。 半导体存储器件还包括操作单元，根据通过地址线施加的操作分配信息，对由读取电路获得的读取数据执行操作，以减少进入修改的读取模式时的存储器访问时间。 此外，半导体存储器件可以可选地管理正常读取模式和修改读取模式，并且允许由操作单元输出的操作结果数据由修改读取模式下的写入电路写入。

公开(公告)号：US09305616B2

公开(公告)日：2016-04-05

申请号：US13943790

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haksoo Yu ,  Dae-Hyun Kim ,  Uksong Kang ,  Chulwoo Park ,  Joosun Choi ,  Hyojin Choi

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/02 ,  G06F12/06 ,  G11C11/403 ,  G11C11/406 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C7/1072 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0638 ,  G11C11/005 ,  G11C11/403 ,  G11C11/40622 ,  G11C29/783 ,  G11C2029/4402

Abstract: A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.

Abstract translation: 提供一种半导体存储单元阵列，其包括第一存储单元阵列区域，该第一存储单元阵列区域包括布置在具有第一运行速度的矩阵中的芯片中的第一组存储单元; 以及第二存储单元阵列区域，包括布置在所述芯片中的行和列的矩阵并具有与所述第一操作速度不同的第二操作速度的第二组存储单元。 通过DRAM控制器的寻址来访问第一和第二存储单元阵列区域。