知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

27 条记录 (耗时 0.02 秒)

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    21.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20170062598A1

    公开(公告)日：2017-03-02

    申请号：US14843231

    申请日：2015-09-02

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： KANG-ILL SEO

    IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

    摘要： A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the first active region and extended in a first direction, and a first gate disposed on the first active region and extended in a second direction crossing the first direction. The first gate covers the first nanowire pattern. The semiconductor device further includes a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern. The first gate includes a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.

    摘要翻译： 半导体器件包括第一有源区，设置在第一有源区中的场绝缘层，设置在第一有源区上并沿第一方向延伸的第一纳米线图案，以及设置在第一有源区上并延伸到第一有源区中的第一栅极 与第一方向交叉的第二方向。 第一个门覆盖了第一个纳米线图案。 半导体器件还包括设置在第一纳米线图案的至少一侧上的源极或漏极外延层。 第一栅极包括设置在第一纳米线图案上并具有第一宽度的第一区域和设置在第一纳米线图案下方并且具有比第一宽度宽的第二宽度的第二区域。

    INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND METHODS OF FORMING THE SAME
    22.
    发明公开
    INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20230142609A1

    公开(公告)日：2023-05-11

    申请号：US17574043

    申请日：2022-01-12

    申请人： Samsung Electronics Co., Ltd.

    发明人： JEONGHYUK YIM ,  KANG-ILL SEO

    IPC分类号： H01L29/423 ,  H01L29/167 ,  H01L27/092 ,  H01L21/8238

    CPC分类号： H01L29/42392 ,  H01L29/167 ,  H01L27/0928 ,  H01L21/823857

    摘要： Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.

    RESISTANCE MEASURING STRUCTURES OF STACKED DEVICES
    23.
    发明申请
    RESISTANCE MEASURING STRUCTURES OF STACKED DEVICES 有权

    公开(公告)号：US20220367521A1

    公开(公告)日：2022-11-17

    申请号：US17382149

    申请日：2021-07-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  MYUNGGIL KANG ,  KANG-ILL SEO

    IPC分类号： H01L27/12 ,  H01L23/535 ,  G01R27/02

    摘要： Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

    SEMICONDUCTOR DEVICE
    25.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170330614A1

    公开(公告)日：2017-11-16

    申请号：US15664591

    申请日：2017-07-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： DAE-JIN KWON ,  KANG-ILL SEO

    IPC分类号： G11C11/419 ,  H01L27/11

    CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

    摘要： Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is connected to the first channel pattern.

    SEMICONDUCTOR DEVICE HAVING A FIN
    27.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A FIN 审中-公开
    具有FIN的半导体器件

    公开(公告)号：US20170018610A1

    公开(公告)日：2017-01-19

    申请号：US15196209

    申请日：2016-06-29

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： SUNG-DAE SUK ,  KANG-ILL SEO

    IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/06

    CPC分类号： H01L29/1054 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

    摘要： Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.

    摘要翻译： 提供一种半导体器件。 半导体器件包括沿第一方向设置在衬底上的翅片。 牺牲层设置在翅片上。 有源层设置在牺牲层上。 沿着与第一方向相交的第二方向设置栅极绝缘层和栅电极。 栅极绝缘层覆盖有源层的大致整个顶部，侧面和底部表面。 源极或漏极区域设置在衬底上的栅电极的至少一侧上。 在第一区域和第二区域中的第一区域和第二区域中的锗的第一浓度高于设置在第一区域和第二区域之间的第三区域中的第二浓度的锗。