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公开(公告)号：US11094745B2
公开(公告)日：2021-08-17
申请号：US16396650
申请日：2019-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byongju Kim , Young-Min Ko , Jonguk Kim , Kwangmin Park , Jeonghee Park , Dongsung Choi
Abstract: A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.
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公开(公告)号：US10818839B2
公开(公告)日：2020-10-27
申请号：US16149507
申请日：2018-10-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeho Jung , Kyoung Sun Kim , Jeonghee Park , Jiho Park , Changyup Park
Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.
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23.发明授权公开(公告)号：US10476000B2
公开(公告)日：2019-11-12
申请号：US15927481
申请日：2018-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee Park , Kyoung Sun Kim
IPC: C23C16/34 , H01L45/00 , H01L27/24 , C23C16/455 , G11C13/00
Abstract: A method of forming a target layer in semiconductor fabrication is disclosed that includes steps of forming a first layer by performing a first process at least one time and forming a second layer by performing a second process at least one time, wherein the first process may include supplying a first source gas, supplying a second source gas several times, and supplying an inert gas several times.
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公开(公告)号：US09520556B2
公开(公告)日：2016-12-13
申请号：US14746039
申请日：2015-06-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hideki Horii , Jeonghee Park , Sugwoo Jung
CPC classification number: H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/141
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a selection element, a lower electrode pattern provided on the selection element to include a horizontal portion and a vertical portion; and a phase-changeable pattern on the lower electrode pattern. The vertical portion may extend from the horizontal portion toward the phase-changeable pattern and have a top surface, whose area is smaller than that of a bottom surface of the phase-changeable pattern.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括选择元件，设置在选择元件上以包括水平部分和垂直部分的下电极图案; 和在下电极图案上的相变图案。 垂直部分可以从水平部分向相变图案延伸，并且具有面积小于可相变图案底面的面积。
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公开(公告)号：US11665914B2
公开(公告)日：2023-05-30
申请号：US17406166
申请日：2021-08-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Si-Ho Song , Jeonghee Park , Changhyun Cho
CPC classification number: H01L27/249 , G11C5/063 , H01L45/06 , H01L45/1253 , H01L45/141
Abstract: A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.
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Patent Agency Ranking
公开(公告)号：US11482670B2
公开(公告)日：2022-10-25
申请号：US16909218
申请日：2020-06-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jiho Park , Kwangmin Park , Jeonghee Park , Changyup Park , Sukhwan Chung
IPC: H01L45/00
Abstract: A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 μs to about 54 μs.
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公开(公告)号：US11387410B2
公开(公告)日：2022-07-12
申请号：US16800123
申请日：2020-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeonghee Park , Kwangmin Park , Jiho Park , Gyuhwan Oh , Jungmoo Lee , Hideki Horii
Abstract: A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.
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公开(公告)号：US20220037401A1
公开(公告)日：2022-02-03
申请号：US17224303
申请日：2021-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee Park , Jonguk Kim , Byeongju Bae
Abstract: A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.
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公开(公告)号：US11037992B2
公开(公告)日：2021-06-15
申请号：US16567094
申请日：2019-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeonghee Park , Dongho Ahn , Changyup Park , Zhe Wu
Abstract: A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.
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公开(公告)号：US20180019281A1
公开(公告)日：2018-01-18
申请号：US15454064
申请日：2017-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ja bin LEE , Jeonghee Park , Dongho Ahn , Zhe Wu , Heeju Shin , Jinwoo Lee
CPC classification number: H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1625
Abstract: A variable resistance memory device may include separate memory cells between separate vertical intersections of first conductive lines extending in a first direction and second conductive lines extending in a second direction intersecting the first direction. A memory cell may include a switching element and a variable resistance structure coupled in series between a first conductive line and a second conductive line. The switching element may include at least one insulative impurity and a chalcogenide material. The variable resistance structure may reversibly switch phases, between a crystalline state and an amorphous state, at a first phase transition temperature, and the switching element may reversibly switch phases, between a crystalline state and an amorphous state, at a second phase transition temperature, where the second phase transition temperature is greater than the first phase transition temperature.
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