公开(公告)号：US09142610B2

公开(公告)日：2015-09-22

申请号：US14074959

申请日：2013-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-Gun Kim ,  Kwang-Tae Hwang ,  Young-Min Ko

IPC: H01L27/00 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/87 ,  H01L28/90

Abstract: A semiconductor device and a method of fabricating the same, the device including a substrate having a transistor formed thereon; a plurality of lower electrodes formed on the substrate; a first supporter and a second supporter on the plurality of lower electrodes; a dielectric film formed on the lower electrode, the first supporter, and the second supporter; and an upper electrode formed on the dielectric film, wherein the first and second supporters are positioned between the lower electrodes, and the first and second supporters include a first material and a second material.

Abstract translation: 一种半导体器件及其制造方法，该器件包括其上形成有晶体管的衬底; 形成在所述基板上的多个下电极; 在所述多个下电极上的第一支撑件和第二支撑件; 形成在下电极，第一支撑体和第二支撑体上的电介质膜; 以及形成在所述电介质膜上的上电极，其中所述第一和第二支撑件位于所述下电极之间，并且所述第一和第二支撑件包括第一材料和第二材料。

公开(公告)号：US10930848B2

公开(公告)日：2021-02-23

申请号：US16415424

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongju Kim ,  Young-Min Ko ,  Jonguk Kim ,  Jaeho Jung ,  Dongsung Choi

IPC: H01L45/00 ,  H01L21/02

Abstract: A method of manufacturing a variable resistance memory device includes: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a preliminary step of supplying a silicon source to an exposed sidewall of the switching element; and a main step of performing a process cycle a plurality of times, the process cycle comprising supplying the silicon source and supplying a reaction gas, A time duration of the supplying the silicon source in the preliminary step is longer than a time duration of the supplying the silicon gas in the process cycle in the main step.

公开(公告)号：US11171287B2

公开(公告)日：2021-11-09

申请号：US16365874

申请日：2019-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Uk Kim ,  Young-Min Ko ,  Byong-Ju Kim ,  Kwang-Min Park ,  Jeong-Hee Park ,  Dong-Sung Choi

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device may include a memory unit including a first electrode disposed on a substrate, a variable resistance pattern disposed on the first electrode and a second electrode disposed on the variable resistance pattern, a selection pattern disposed on the memory unit, and a capping structure covering a sidewall of the selection pattern. The capping structure may include a first capping pattern and a second capping pattern sequentially stacked on at least one sidewall of the selection pattern. The first capping pattern may be silicon pattern, and the second capping pattern may include a nitride.

公开(公告)号：US09263536B2

公开(公告)日：2016-02-16

申请号：US14062138

申请日：2013-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Gun Kim ,  Young-Min Ko ,  Kwang-Tae Hwang

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/423 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L28/92

Abstract: Methods include sequentially forming a first mold film, a first support film, a second mold film, and a second support film on a substrate, forming a contact hole through the second support film, the second mold film, the first support film and the first mold film, forming an electrode in the contact hole, and removing portions of the second support film, the second mold film and the first mold film to leave a portion of the first support film as a first support pattern surrounding the electrode and to leave a portion of the second support film as a second support pattern surrounding the electrode.

Abstract translation: 方法包括在基板上依次形成第一模具膜，第一支撑膜，第二模塑膜和第二支撑膜，通过第二支撑膜，第二模制膜，第一支撑膜和第一支撑膜形成接触孔 模具膜，在接触孔中形成电极，以及去除第二支撑膜，第二模具膜和第一模具膜的部分，以使第一支撑膜的一部分作为围绕电极的第一支撑图案，并且留下一个 第二支撑膜的一部分作为围绕电极的第二支撑图案。

公开(公告)号：US11094745B2

公开(公告)日：2021-08-17

申请号：US16396650

申请日：2019-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongju Kim ,  Young-Min Ko ,  Jonguk Kim ,  Kwangmin Park ,  Jeonghee Park ,  Dongsung Choi

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.

公开(公告)号：US20140134839A1

公开(公告)日：2014-05-15

申请号：US14062138

申请日：2013-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Gun Kim ,  Young-Min Ko ,  Kwang-Tae Hwang

IPC: H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L28/92

Abstract: Methods include sequentially forming a first mold film, a first support film, a second mold film, and a second support film on a substrate, forming a contact hole through the second support film, the second mold film, the first support film and the first mold film, forming an electrode in the contact hole, and removing portions of the second support film, the second mold film and the first mold film to leave a portion of the first support film as a first support pattern surrounding the electrode and to leave a portion of the second support film as a second support pattern surrounding the electrode.

Abstract translation: 方法包括在基板上依次形成第一模具膜，第一支撑膜，第二模塑膜和第二支撑膜，通过第二支撑膜，第二模制膜，第一支撑膜和第一支撑膜形成接触孔 模具膜，在接触孔中形成电极，以及去除第二支撑膜，第二模具膜和第一模具膜的部分，以使第一支撑膜的一部分作为围绕电极的第一支撑图案，并且留下一个 第二支撑膜的一部分作为围绕电极的第二支撑图案。

公开(公告)号：US20230230937A1

公开(公告)日：2023-07-20

申请号：US17930820

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunuk Jeon ,  Yuseon Kang ,  Young-Min Ko ,  Dong Young Kim

IPC: H01L23/00 ,  H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L23/562 ,  H01L23/535 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. A semiconductor device includes a substrate, a cell array structure including a plurality of electrodes stacked on the substrate, a vertical channel structure that penetrates the cell array structure and is connected to the substrate, a conductive pad in an upper portion of the vertical channel structure, an interlayer insulating layer on the cell array structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a first stress release layer between the cell array structure and the bit line on a top surface of the interlayer insulating layer. The first stress release layer includes organosilicon polymer, and a carbon concentration of the first stress release layer is higher than that of the interlayer insulating layer.

公开(公告)号：US11456414B2

公开(公告)日：2022-09-27

申请号：US16416472

申请日：2019-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonguk Kim ,  Young-Min Ko ,  Byongju Kim ,  Jaeho Jung ,  Dongsung Choi

IPC: H01L27/24 ,  H01L45/00

Abstract: A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.

公开(公告)号：US10586709B2

公开(公告)日：2020-03-10

申请号：US16030212

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Min Ko ,  Hyuk Woo Kwon ,  Jun-Won Lee

IPC: H01L21/308 ,  G03F7/20 ,  H01L21/033 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.