Method of startup sequence for a panel interface
    21.
    发明授权
    Method of startup sequence for a panel interface 有权
    面板界面的启动顺序方法

    公开(公告)号:US09571155B2

    公开(公告)日:2017-02-14

    申请号:US14832938

    申请日:2015-08-21

    CPC classification number: H04B3/238 H04L7/0008

    Abstract: A system for starting a point-to-multi-point serial communications system. The system includes a transmitter having a sync connection and a plurality of data outputs and a plurality of receivers, each of the plurality of receiver having a sync connection and a data input; the data input of each of the plurality of receivers being connected to a respective one of the plurality of data outputs of the transmitter; and the sync connection of the transmitter being connected, by a conductor, to the sync connection of each of the plurality of receivers, each of the plurality of receivers comprising a first impedance and a first switch, the first impedance and the first switch configured to establish, when the first switch is closed, a current path between the sync connection of the receiver and a first voltage source in the receiver.

    Abstract translation: 用于启动点对多点串行通信系统的系统。 该系统包括具有同步连接和多个数据输出和多个接收器的发射机,多个接收机中的每一个具有同步连接和数据输入; 所述多个接收机中的每一个的数据输入端连接到所述发射机的所述多个数据输出中的相应一个; 以及由导体连接到所述多个接收机中的每一个的同步连接的所述发射机的同步连接,所述多个接收机中的每一个包括第一阻抗和第一开关,所述第一阻抗和所述第一开关被配置为 当第一开关闭合时,建立接收器的同步连接和接收器中的第一电压源之间的电流路径。

    PVT tolerant differential circuit
    22.
    发明授权
    PVT tolerant differential circuit 有权
    PVT容差差分电路

    公开(公告)号:US09344305B2

    公开(公告)日:2016-05-17

    申请号:US14254813

    申请日:2014-04-16

    Abstract: An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.

    Abstract translation: 一种自动校准的差分放大器,包括:输入级差分放大器,被配置为接收输入差分信号,差分放大输入差分信号以产生输入级输出差分信号,并具有输入级偏置电流; 以及复制级差分放大器,被配置为响应于过程或环境变化自动校准输入级偏置电流。 差分放大器可以包括在例如比较器和多电平接收器中。

    PVT TOLERANT DIFFERENTIAL CIRCUIT
    23.
    发明申请
    PVT TOLERANT DIFFERENTIAL CIRCUIT 有权
    PVT耐受差分电路

    公开(公告)号:US20140314173A1

    公开(公告)日:2014-10-23

    申请号:US14254813

    申请日:2014-04-16

    Abstract: An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.

    Abstract translation: 一种自动校准的差分放大器,包括:输入级差分放大器,被配置为接收输入差分信号,差分放大输入差分信号以产生输入级输出差分信号,并具有输入级偏置电流; 以及复制级差分放大器,被配置为响应于过程或环境变化自动校准输入级偏置电流。 差分放大器可以包括在例如比较器和多电平接收器中。

    Real-time DC-balance aware AFE offset cancellation

    公开(公告)号:US11881969B2

    公开(公告)日:2024-01-23

    申请号:US17885001

    申请日:2022-08-10

    Abstract: A receiver for a serial data link, including an analog front end (AFE) including a continuous-time linear equalizer (CTLE) configured to receive an input signal from a transmitter, the CTLE including a first output node; a second output node; a plurality of programmable tail current sources configured to adjust a direct current (DC) offset between the first output node and the second output node; and a calibration circuit including: a slicer configured to output a difference between a first average output voltage corresponding to the first output node and a second average output, voltage corresponding to the second output node; and a calibration counter configured to increment or decrement an offset count based on the difference, wherein the plurality of programmable tail current sources are adjusted based on a value of the offset count.

    SYSTEMS AND METHODS FOR TRANSITION ENCODING COMPATIBLE PAM4 ENCODING

    公开(公告)号:US20230081418A1

    公开(公告)日:2023-03-16

    申请号:US17476387

    申请日:2021-09-15

    Abstract: A system includes a first encoder configured to receive first input bits and generate a first stream of first bits based on the first input bits, a bit generator configured to receive second inputs bits and generate a second stream of second bits based on the second input bits, and a PAM4 transmitter configured to receive the first stream of first bits and the second stream of second bits, and generate PAM4 symbols based at least on the first stream of first bits.

    SYSTEMS AND METHODS FOR TRANSITION ENCODING WITH PROTECTED KEY

    公开(公告)号:US20230036390A1

    公开(公告)日:2023-02-02

    申请号:US17516604

    申请日:2021-11-01

    Abstract: A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.

    MULTI-PIXEL COLLECTIVE ADJUSTMENT FOR STEADY STATE TRACKING OF PARAMETERS

    公开(公告)号:US20220093041A1

    公开(公告)日:2022-03-24

    申请号:US17183061

    申请日:2021-02-23

    Abstract: A method for compensating for transistor aging in a display device is presented. The method entails dividing pixels into a plurality of groups including a first group, the first group including Z pixels wherein Z>1, sampling a pixel current for each pixel in a subset of pixels in the first group, the subset including M pixels wherein 1≤M≤Z, determining an ErrorM using the sampled pixel current for the M pixels and a predefined reference current, and adjusting an input voltage for a transistor in more than one of the Z pixels based on the ErrorM. The adjusting of the input voltage may include generating a modified voltage Vd, wherein Vd=A*Vin+B, and each of A and B is determined using ΣM sign(Errorm).

    Smart gate display logic
    30.
    发明授权

    公开(公告)号:US11114057B2

    公开(公告)日:2021-09-07

    申请号:US16183488

    申请日:2018-11-07

    Abstract: Provided is a method of reducing power consumption by a display device including a display logic for processing pixel data, and a display panel including a plurality of pixels, the method including receiving the pixel data corresponding to the plurality of pixels, determining whether a number of consecutive pixels of the plurality of pixels that correspond to identical data of the pixel data reaches a threshold number, and powering down the display logic when the number of consecutive pixels exceeds the threshold number.

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