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公开(公告)号：US20200091779A1
公开(公告)日：2020-03-19
申请号：US16564086
申请日：2019-09-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jangwoo LEE , Taeseon KIM , Taeho WANG , Soonkyu JANG , Sunmi JIN , Jihoon HA
Abstract: According to certain embodiments, an electronic device comprises a plurality of coils configured to transmit charging power; a communication circuit; at least one processor; and at least one memory. The at least one memory stores instructions that, when executed by the at least one processor, causes the at least one processor to perform a plurality of operations. The plurality of operations comprises transmitting a first signal for requesting device-related information to a plurality of external electronic devices through the communication circuit, receiving a corresponding plurality of first response signals in response to the first signal from the plurality of external electronic devices through the communication circuit, selecting at least one external electronic device from among the plurality of external electronic devices on the basis of the plurality of first response signals, and upon selecting the at least one selected external electronic device, transmitting a second signal that indicates the at least one selected external electronic device and comprises at least information associated with the plurality of external electronic devices to the plurality of external electronic devices via the communication circuit.
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公开(公告)号：US20170295469A1
公开(公告)日：2017-10-12
申请号：US15482123
申请日：2017-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Choonkyoung MOON , Jangwoo LEE , Ja Ok KOO , Hyunsoo NAH , Eunkyung YOO
CPC classification number: H04W4/029 , H04L12/282 , H04L67/12 , H04L67/18 , H04L2012/285
Abstract: The present disclosure relates to an electronic device and an operating method thereof. The electronic device includes a memory configured to store at least one expected movement path, and a processor configured to confirm a first location of a user, predict a second location on a basis of the first location and a pre-stored at least one expected movement path, and provide an information service providing signal to at least one external device present in the second location. The method includes confirming a first location of a user, predicting a second location on a basis of the first location and a pre-stored at least one expected movement path, and providing an information service providing signal to at least one external device present in the second location.
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公开(公告)号：US20240429110A1
公开(公告)日：2024-12-26
申请号：US18667838
申请日：2024-05-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jangwoo LEE , Hyunglak MA , Jiyong PARK , Jongbo SHIM
IPC: H01L23/16 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/10
Abstract: A semiconductor package includes a lower package having opposite first and second lower package sides that extend in a first direction; an upper package stacked on the lower package by conductive connection members, the upper package having opposite first and second upper package sides that extend in the first direction, wherein the second upper package side is spaced apart from the second lower package side by a predetermined distance to define an underfill region on an upper surface of the lower package; and an underfill member extending from the underfill region on the upper surface of the lower package to fill a space between the lower package and the upper package.
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公开(公告)号：US20230352460A1
公开(公告)日：2023-11-02
申请号：US18091072
申请日：2022-12-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eunsu LEE , Jangwoo LEE , Doyoung JANG
IPC: H01L25/10 , H01L23/498 , H01L23/31 , H01L23/538 , H01L23/00
CPC classification number: H01L25/105 , H01L23/49811 , H01L23/49838 , H01L23/49822 , H01L23/3128 , H01L23/5383 , H01L23/5389 , H01L24/16 , H01L24/81 , H01L24/13 , H01L2224/16227 , H01L2224/81385 , H01L2224/13111 , H01L2224/13116 , H01L2224/13155 , H01L2224/13144 , H01L2224/13139 , H01L2224/13147 , H01L2224/13124 , H01L2224/13113 , H01L2224/81447
Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip provided on the first package substrate, an interposer provided on the first semiconductor chip, and a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer, the interposer includes a first recess vertically overlapping the first semiconductor chip in a lower portion of the interposer, and a lower surface of the interposer defining the first recess is higher than an upper surface of the vertical conductive structure.
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公开(公告)号：US20230130530A1
公开(公告)日：2023-04-27
申请号：US18088036
申请日：2022-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chunhyoung PARK , Jangwoo LEE , Seokjin LIM , Yujin LIM , Jinhoon CHO
Abstract: An electronic apparatus according to various embodiments of the present disclosure comprises: a first display foldable with respect to at least one axis; a sensor configured to detect the folding state of the first display; and a processor operatively connected to the first display and the sensor, wherein the processor is configured to: detect the folding state of the first display using the sensor; determine the display area of the first display based on the folding state of the first display; select an operating system (OS) corresponding to the folding state of the first display; and display a user interface (UI) on the display area of the first display, the user interface being generated in the operating system.
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Patent Agency Ranking
公开(公告)号：US20220350541A1
公开(公告)日：2022-11-03
申请号：US17867008
申请日：2022-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daehoon NA , Jeongdon IHM , Jangwoo LEE , Byunghoon JEONG
Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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27.发明申请公开(公告)号：US20220083237A1
公开(公告)日：2022-03-17
申请号：US17536506
申请日：2021-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daehoon NA , Jangwoo LEE , Jeongdon IHM
IPC: G06F3/06
Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.
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公开(公告)号：US20210104267A1
公开(公告)日：2021-04-08
申请号：US17001941
申请日：2020-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon JEONG , Kyungtae KANG , Jangwoo LEE , Jeongdon IHM
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号：US20210103407A1
公开(公告)日：2021-04-08
申请号：US17031069
申请日：2020-09-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daehoon NA , Jeongdon IHM , Jangwoo LEE , Byunghoon JEONG
Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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30.发明申请公开(公告)号：US20210072902A1
公开(公告)日：2021-03-11
申请号：US16861802
申请日：2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daehoon NA , Jangwoo LEE , Jeongdon IHM
IPC: G06F3/06
Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.
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