公开(公告)号：US09954052B2

公开(公告)日：2018-04-24

申请号：US14958146

申请日：2015-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L21/8238

CPC classification number: H01L29/0615 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/1054 ,  H01L29/16

Abstract: A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.

公开(公告)号：US09577097B2

公开(公告)日：2017-02-21

申请号：US14806782

申请日：2015-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Lee

IPC: H01L29/78 ,  H01L29/737 ,  H01L29/165 ,  H01L29/66 ,  H01L29/267 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7378

Abstract: A semiconductor device having a stressor is provided. A first trench and a second trench spaced apart from each other are formed in a substrate. A channel area is defined between the first trench and the second trench. A gate dielectric layer is formed on the channel area. A gate electrode is formed on the gate dielectric layer. The stressor includes a plurality of semiconductor layers formed in the first trench and the second trench and a plurality of interlayers formed between the semiconductor layers. Sidewalls of the first trench and the second trench are v-shaped (e.g., have a shape).

Abstract translation: 提供了具有应力源的半导体器件。 在衬底中形成彼此间隔开的第一沟槽和第二沟槽。 在第一沟槽和第二沟槽之间限定沟道区域。 栅极电介质层形成在沟道区上。 在栅极电介质层上形成栅电极。 应力器包括形成在第一沟槽和第二沟槽中的多个半导体层以及形成在半导体层之间的多个中间层。 第一沟槽和第二沟槽的侧壁是v形的（例如，具有<或>形状）。