公开(公告)号：US08941216B2

公开(公告)日：2015-01-27

申请号：US13749727

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

Abstract translation: 本发明构思提供了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面开口并部分地穿透衬底的通孔，在通孔的底表面上形成具有第一厚度的通孔绝缘层，并且小于第一厚度的第二厚度 在通孔的内侧壁上的厚度，在形成通孔绝缘层的通孔中形成通孔，并使基板的底表面凹陷以露出通孔。 形成通孔绝缘层可以包括在基板上形成可流动层，并且将可流动层转化为具有第一厚度的第一可流动化学气相沉积层，其在通孔的底表面上。

公开(公告)号：US20130207241A1

公开(公告)日：2013-08-15

申请号：US13749727

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheun Choi

IPC: H01L23/522

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

Abstract translation: 本发明构思提供了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面开口并部分地穿透衬底的通孔，在通孔的底表面上形成具有第一厚度的通孔绝缘层，并且小于第一厚度的第二厚度 在通孔的内侧壁上的厚度，在形成通孔绝缘层的通孔中形成通孔，并使基板的底表面凹陷以露出通孔。 形成通孔绝缘层可以包括在基板上形成可流动层，并且将可流动层转化为具有第一厚度的第一可流动化学气相沉积层，其在通孔的底表面上。

公开(公告)号：US12249557B2

公开(公告)日：2025-03-11

申请号：US17581084

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Ha Oh ,  Kwang Jin Moon ,  Ho-Jin Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L27/088

Abstract: A semiconductor device comprises a substrate that including a frontside comprising an active region and a backside opposite to the frontside, an electronic element on the active region, a frontside wiring structure electrically connected to the electronic element on the frontside of the substrate, and a backside wiring structure electrically connected to the electronic element on the backside of the substrate. The backside wiring structure includes a plurality of backside wiring patterns sequentially stacked on the backside of the substrate, and a super via pattern that intersects and extends through at least one layer of the plurality of backside wiring patterns.

公开(公告)号：US20240006362A1

公开(公告)日：2024-01-04

申请号：US18155988

申请日：2023-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Bin Seo ,  Seok Ho Kim ,  Kwang Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/14519 ,  H01L2224/1403 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/13083 ,  H01L2224/05655 ,  H01L2224/13155 ,  H01L2224/13147 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13144

Abstract: A semiconductor device including a substrate, a wiring pattern in the substrate, a passivation layer on the substrate, the passivation layer and the substrate including a first recess penetrating a part of each of the passivation layer and the substrate and extending toward the wiring pattern, a post connected to the wiring pattern and including a first portion within the first recess and a second portion on the first portion and protruding from a top surface of the passivation layer, a signal bump including a seed layer on the post, a lower bump on the seed layer, and an upper bump on the lower bump, and a heat transfer bump apart from the signal bump, electrically insulated from the wiring pattern, and including another seed layer on the passivation layer, another lower bump on the another seed layer, and another upper bump on the another lower bump may be provided.

公开(公告)号：US10978655B2

公开(公告)日：2021-04-13

申请号：US16562434

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Kwang-Jin Moon ,  Nae-In Lee ,  Ho-Jin Lee

IPC: H01L23/485 ,  H01L51/44 ,  H01L25/065 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00 ,  H01L51/00 ,  H01L21/768 ,  H01L25/00 ,  B82Y99/00 ,  B82Y10/00 ,  H01L25/18 ,  H01L27/146

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US10833032B2

公开(公告)日：2020-11-10

申请号：US16052383

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min Son ,  Jeong-Gi Jin ,  Jin-Ho An ,  Jin-Ho Chun ,  Kwang-Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

公开(公告)号：US09583373B2

公开(公告)日：2017-02-28

申请号：US13964433

申请日：2013-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Gilheyun Choi

IPC: H01L21/683 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L21/78 ,  H01L2224/81

Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.

Abstract translation: 晶片载体包括具有设置在基部的中心处的空腔的基部和沿着基部的边缘延伸并远离基部的边缘的外侧壁以限定空腔。 空腔构造成填充有粘合剂层。 晶片载体构造成在基底的空腔中与粘合剂层结合到晶片，使得外侧壁面向并与晶片的边缘接触并且空腔面向晶片的中心。

公开(公告)号：US09530706B2

公开(公告)日：2016-12-27

申请号：US14669291

申请日：2015-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-Kyu Kang ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  Ju-il Choi ,  Yi Koan Hong

IPC: H01L25/065 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract translation: 提供具有芯片堆叠和互连端子的半导体器件。 芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。 互连端子电耦合到芯片堆叠。 第一半导体芯片包括第一正面和第一背面。 第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。 第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。 第一前表面和第二前表面彼此面对。 第三前表面和第二后侧表面彼此面对。

公开(公告)号：US20160163590A1

公开(公告)日：2016-06-09

申请号：US14956869

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung Jung ,  Seong-Min Son ,  Jin-Ho An ,  Byung-Lyul Park ,  Ji-Soon Park ,  Ho-Jin Lee

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L24/03 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/114 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599

Abstract: Disclosed is a method of manufacturing a semiconductor device. A preliminary wafer-carrier assembly is formed in such a way that a wafer structure having a plurality of via structures is adhered to a light-penetrating carrier by a photodegradable adhesive. A wafer-carrier assembly having an optical shielding layer for inhibiting or preventing a light penetration is formed such that the wafer structure, the carrier and the adhesive are covered with the optical shielding layer except for the backside of the wafer structure through which the via structures are exposed. An interconnector is formed on the backside of the wafer structure such that the via structures make contact with the interconnector, and the wafer structure and the carrier are separated from each other by irradiating a light to the wafer-carrier assembly. Accordingly, the adhesive is inhibited or prevented from being dissolved during a plasma process on the wafer-carrier assembly.

Abstract translation: 公开了半导体器件的制造方法。 初步的晶片载体组件形成为具有多个通路结构的晶片结构通过可光降解的粘合剂粘附到透光载体上。 形成具有用于抑制或防止光穿透的光学屏蔽层的晶片载体组件，使得晶片结构，载体和粘合剂被除了晶片结构的背面之外的光学屏蔽层覆盖，通过该晶片结构， 被暴露。 在晶片结构的背面形成互连器，使得通孔结构与互连器接触，并且通过向晶片载体组件照射光而使晶片结构和载体彼此分离。 因此，在晶片载体组件的等离子体处理中，粘合剂被抑制或防止溶解。

公开(公告)号：US09362172B2

公开(公告)日：2016-06-07

申请号：US14566828

申请日：2014-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.