公开(公告)号：US20130285019A1

公开(公告)日：2013-10-31

申请号：US13833987

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Dongwon KIM ,  Dae Mann Kim ,  Yoon-Ha Jeong ,  Sooyoung Park ,  Chan-Hoon Park ,  Rock-Hyun Baek ,  Sang-Hyun Lee

IPC: H01L29/775 ,  H01L29/78

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/78 ,  Y10S977/742

Abstract: Provided is a field effect transistor including a drain region, a source region, and a channel region. The field effect transistor may further include a gate electrode on or surrounding at least a portion of the channel region, and a gate dielectric layer between the channel region and the gate electrode. A portion of the channel region adjacent the source region has a sectional area smaller than that of another portion of the channel region adjacent the drain region.

Abstract translation: 提供了包括漏极区域，源极区域和沟道区域的场效应晶体管。 场效应晶体管还可以包括在沟道区的至少一部分上或围绕沟道区的至少一部分的栅电极，以及沟道区和栅电极之间的栅介质层。 与源极区域相邻的沟道区域的一部分的截面积小于与漏极区域相邻的沟道区域的另一部分的截面面积。

公开(公告)号：US20250144821A1

公开(公告)日：2025-05-08

申请号：US19013201

申请日：2025-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeongsup BYEON ,  Inwook KOO ,  Dongwon KIM ,  Minyoung KIM ,  Yi JIN ,  Jongkyu KIM ,  Jinho SO ,  Byungjun AN ,  Yinghu XU ,  Beomsoo HWANG

IPC: B25J19/02 ,  B25J9/16 ,  B25J11/00 ,  B25J15/00 ,  B65G1/137 ,  F17C13/04 ,  G06K7/14

Abstract: A gas supply system includes a loading/unloading stage including a cradle loader where a cradle loaded with a gas container is loaded, a test buffer chamber is configured to test the gas container, and a loading/unloading robot configured to transfer the gas container between the cradle and the test buffer chamber. A gas supply stage includes a storage queue configured to temporarily store the gas container, a gas supply cabinet where the gas container is mounted, and a transfer robot configured to transfer the gas container between the test buffer chamber and the storage queue and between the storage queue and the gas supply cabinet.

公开(公告)号：US20240096995A1

公开(公告)日：2024-03-21

申请号：US18231841

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Myunggil KANG ,  Dongwon KIM ,  Younggwon KIM ,  Hyumin YOO ,  Soojin JEONG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device, may include an active region extending in a first direction; a plurality of channel layers on the active region to be spaced apart from each other; a gate structure, surrounding the plurality of channel layers, respectively; and source/drain regions on the active region on at least one side of the gate structure, and contacting the plurality of channel layers, wherein the gate structure may include an upper portion on an uppermost channel layer among the plurality of channel layers and lower portions between each of the plurality of channel layers in a region vertically overlapping the plurality of channel layers, wherein a width of each of the plurality of channel layers in the first direction may be less than a width of lower portions of the gate structure, adjacent to the respective channel layers among the lower portions of the gate structure in the first direction.

公开(公告)号：US20240038763A1

公开(公告)日：2024-02-01

申请号：US18486331

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20210091211A1

公开(公告)日：2021-03-25

申请号：US16857621

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dongwon KIM ,  Minyi KIM ,  Keun Hwi CHO

IPC: H01L29/732 ,  H01L21/8228 ,  H01L21/8238 ,  H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

公开(公告)号：US20170194330A1

公开(公告)日：2017-07-06

申请号：US15255652

申请日：2016-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun LEE ,  TaeYong KWON ,  Dongwon KIM

IPC: H01L27/11 ,  H01L29/417 ,  H01L27/092

Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.