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    SEMICONDUCTOR DEVICE
    21.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220036961A1

    公开(公告)日：2022-02-03

    申请号：US17382923

    申请日：2021-07-22

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shinji TANAKA ,  Yuichiro ISHII ,  Makoto YABUUCHI

    IPC: G11C29/50 ,  G11C11/419 ,  G11C5/06

    Abstract: A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

    SEMICONDUCTOR DEVICE
    22.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190198074A1

    公开(公告)日：2019-06-27

    申请号：US16192272

    申请日：2018-11-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII

    IPC: G11C8/08 ,  G11C11/417 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  G11C8/16 ,  H01L27/11

    Abstract: A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.

    MULTI-PORT MEMORY AND SEMICONDUCTOR DEVICE
    23.
    发明申请
    MULTI-PORT MEMORY AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180301184A1

    公开(公告)日：2018-10-18

    申请号：US16013514

    申请日：2018-06-20

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII

    IPC: G11C11/418 ,  G11C11/412 ,  G11C7/10 ,  G11C11/419 ,  G11C8/16

    CPC classification number: G11C11/418 ,  G11C7/1018 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419

    Abstract: A memory circuit includes: a control circuit generating first and second start signals within a single signal cycle of an input clock signal; an address control circuit coupled to a plurality of address ports for receiving a plurality of address signals and activating one of word lines corresponding to one of the address signals based on the first or second start signals; and a data input/output circuit for writing or reading data by selecting one of memory cells coupled to the activated word line. The control circuit includes: a start signal generation unit that generates the first start signal in response to a first pulse signal and the second start signal in response to a second pulse signal, and a pulse signal generation unit that generates the first pulse signal in response to the input clock signal and the second signal in response to the first start signal.

    SEMICONDUCTOR DEVICE
    24.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170309326A1

    公开(公告)日：2017-10-26

    申请号：US15513138

    申请日：2015-03-31

    Applicant: Renesas Electronics Corporation

    Inventor： Yohei SAWADA ,  Makoto YABUUCHI ,  Yuichiro ISHII

    IPC: G11C11/417

    CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413

    Abstract: A semiconductor device includes a SRAM circuit. The SRAM circuit includes: a memory array having a plurality of memory cells arranged in a matrix; a ground interconnection commonly connected to each of the memory cells; and a first potential control circuit for controlling a potential of the ground interconnection depending on an operation mode. The first potential control circuit includes a first NMOS transistor and a first PMOS transistor connected in parallel to each other between a around node providing a ground potential and the ground interconnection.

    Semiconductor Device, Test Program, and Test Method
    28.
    发明申请
    Semiconductor Device, Test Program, and Test Method 有权
    半导体器件，测试程序和测试方法

    公开(公告)号：US20160254062A1

    公开(公告)日：2016-09-01

    申请号：US15000027

    申请日：2016-01-18

    Applicant: Renesas Electronics Corporation

    Inventor： Atsushi MIYANISHI ,  Yuichiro ISHII ,  Yoshisato YOKOYAMA

    IPC: G11C29/04 ,  G11C11/417

    CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50

    Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed.An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

    Abstract translation: 当进行常温下的筛选试验而不是SRAM的低温筛选试验时，过度杀虫剂被降低，并且由于局部变化而导致的缺陷流出的风险被抑制。 包括字线，位线对，存储单元和驱动位线对的驱动电路的SRAM具有能够将位线对的一个位线驱动为高电平（VDD）电位的功能 并在将数据写入存储单元时将其他位线驱动为比正常写入的低电平（VSS）电位稍高的中间电位（VSS +几十mV至几十mV）。

    SEMICONDUCTOR STORAGE DEVICE
    29.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20160071576A1

    公开(公告)日：2016-03-10

    申请号：US14847365

    申请日：2015-09-08

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII

    IPC: G11C11/419

    CPC classification number: G11C11/418 ,  G11C5/147 ,  G11C7/20 ,  G11C11/412 ,  G11C11/419

    Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.

    Abstract translation: 所公开的发明提供了一种半导体存储装置，其独立于上电序列而不产生故障。 半导体存储装置包括用于存储单元的第一电源，独立于第一电源而导通的第二电源，并且被提供给电耦合到存储单元的外围电路，以及字线电平固定电路 用于固定根据第一电源的开启而工作的字线的电平。 字线电平固定电路包括多个电平固定晶体管，它们分别被提供以对应于字线并且被设置在一个字线和一个固定电位之间，而电平固定控制电路根据输入端 响应于第二电源的接通的信号。

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