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公开(公告)号:US20150022024A1
公开(公告)日:2015-01-22
申请号:US13944709
申请日:2013-07-17
Applicant: Qualcomm Incorporated
Inventor: Marc Gerald Dicicco , Xiangdong Zhang , Xinwei Wang
IPC: H03K17/16
CPC classification number: H03K17/16 , H03K17/162
Abstract: Exemplary embodiments are related to switch linearizer. A device may include at least one switch. The device may further include a linearizer coupled to the at least one switch and configured to cancel at least a portion of distortion generated by the at least one switch in an off-state.
Abstract translation: 示例性实施例涉及开关线性化器。 设备可以包括至少一个开关。 该装置还可以包括耦合到该至少一个开关的线性化装置,并且被配置为在断开状态下消除由至少一个开关产生的失真的至少一部分。
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公开(公告)号:US08897727B2
公开(公告)日:2014-11-25
申请号:US13828714
申请日:2013-03-14
Applicant: QUALCOMM Incorporated
Inventor: Xinwei Wang , Yongrong Zuo , Xiangdong Zhang , Marc Gerald DiCicco
CPC classification number: H04B17/0062 , G01R21/10 , G01R21/14 , G01R29/0871 , H03F3/245 , H03F3/45183 , H03F3/45188 , H03F2200/447 , H03F2200/453 , H03F2200/456 , H03F2200/465 , H03F2203/45112 , H03F2203/45156 , H03F2203/45292 , H03F2203/45302 , H03F2203/45481 , H03G1/04 , H03G3/3036 , H04B17/21
Abstract: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.
Abstract translation: 公开了具有温度补偿并且具有提高的温度精度的功率检测器。 在本公开的一个方面,通过改变功率检测器内的MOS晶体管的栅极和漏极电压来降低功率检测器的增益随温度的变化。 在示例性设计中,一种装置包括至少一个MOS晶体管,其接收输入信号,基于功率检测增益来检测输入信号的功率,并提供表示输入信号功率的输出信号。 至少一个MOS晶体管被施加可变栅极偏置电压和可变漏极偏置电压,以便减小功率检测增益随温度的变化。 至少一个附加MOS晶体管可以接收第二可变栅极偏置电压,并为至少一个MOS晶体管提供可变漏极偏置电压。
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公开(公告)号:US11824500B2
公开(公告)日:2023-11-21
申请号:US17129384
申请日:2020-12-21
Applicant: Qualcomm Incorporated
Inventor: Xiangdong Zhang , Ryan Scott Castro Spring , Marco Cassia , Yan Kit Gary Hau , Kanan Gandhi , Robert Wilson
CPC classification number: H03F1/0227 , H03F3/195 , H03F2200/451
Abstract: An apparatus is disclosed for waveform-tailored average power tracking. In an example aspect, the apparatus includes an amplifier, a power converter, and an average power tracking module. The amplifier is configured to amplify radio-frequency signals using a supply voltage. The radio-frequency signals have different waveforms. The power converter is coupled to the amplifier and configured to provide the supply voltage. The average power tracking module is coupled to the power converter and configured to adjust the supply voltage according to the different waveforms to cause the supply voltage to vary across at least two waveforms of the different waveforms for related average output powers.
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公开(公告)号:US09813043B2
公开(公告)日:2017-11-07
申请号:US15079789
申请日:2016-03-24
Applicant: QUALCOMM Incorporated
Inventor: Chengjie Zuo , Daeik D. Kim , Je-Hsiung Lan , Jonghae Kim , Mario Francisco Velez , Changhan Yun , David F. Berdy , Robert P. Mikulka , Matthew M. Nowak , Xiangdong Zhang , Puay H. See
CPC classification number: H03H7/461 , H03H3/00 , H03H7/0115 , H03H7/463 , Y10T29/49016
Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
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公开(公告)号:US09449753B2
公开(公告)日:2016-09-20
申请号:US14155244
申请日:2014-01-14
Applicant: QUALCOMM Incorporated
Inventor: Daeik Daniel Kim , Chengjie Zuo , Changhan Hobie Yun , Mario Francisco Velez , Robert Paul Mikulka , Xiangdong Zhang , Jonghae Kim , Je-Hsiung Lan
CPC classification number: H01F41/041 , H01F17/0013 , H01F27/2804 , H01F41/042 , H01F2017/0053 , H01F2017/0073 , H01F2027/2809
Abstract: A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.
Abstract translation: 特定器件包括衬底和耦合到衬底的螺旋电感器。 螺旋电感器包括覆盖第一导电螺旋的第一导电螺旋和第二导电螺旋。 螺旋电感器的最内圈的第一部分在垂直于衬底的方向上具有第一厚度。 最内圈的第一部分包括第一导电螺旋的第一部分,并且不包括第二导电螺旋。 最内圈的第二部分包括第二导电螺旋的第一部分。 螺旋电感器的最外圈的一部分在垂直于衬底的方向上具有大于第一厚度的第二厚度。 最外圈的一部分包括第一导电螺旋的第二部分和第二导电螺旋的第二部分。
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公开(公告)号:US20140266518A1
公开(公告)日:2014-09-18
申请号:US13826265
申请日:2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor: Xinwei Wang , Xiangdong Zhang , Marc Gerald Dicicco
IPC: H03H11/24
Abstract: A step attenuator with constant input capacitance and having good performance is disclosed. In an exemplary design, an apparatus includes a step attenuator having a constant input capacitance for different amounts of attenuation. The step attenuator receives an input signal, provides a variable amount of attenuation for the input signal, and provides an output signal. The step attenuator may include a plurality of attenuator sections coupled in series. Each attenuator section may include a plurality of capacitors and may have the constant input capacitance. At least one of the plurality of attenuator sections may be selected or unselected to obtain a selected amount of attenuation for the step attenuator. An attenuator section may provide a predetermined amount of attenuation or a variable amount of attenuation when selected. The apparatus may further include a power detector that receives and determines the power of the output signal from the step attenuator.
Abstract translation: 公开了具有恒定输入电容并具有良好性能的阶梯衰减器。 在示例性设计中,装置包括具有用于不同衰减量的恒定输入电容的阶梯衰减器。 步进衰减器接收输入信号,为输入信号提供可变量的衰减,并提供输出信号。 阶梯衰减器可以包括串联耦合的多个衰减器部分。 每个衰减器部分可以包括多个电容器并且可以具有恒定的输入电容。 可以选择或取消选择多个衰减器部分中的至少一个以获得用于步进衰减器的选定量的衰减。 衰减器部分可以在选择时提供预定量的衰减或可变量的衰减。 该装置还可以包括功率检测器,其接收并确定来自阶梯衰减器的输出信号的功率。
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公开(公告)号:US20130324062A1
公开(公告)日:2013-12-05
申请号:US13828714
申请日:2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor: Xinwei Wang , Yongrong Zuo , Xiangdong Zhang , Marc Gerald DiCicco
IPC: H04B17/00
CPC classification number: H04B17/0062 , G01R21/10 , G01R21/14 , G01R29/0871 , H03F3/245 , H03F3/45183 , H03F3/45188 , H03F2200/447 , H03F2200/453 , H03F2200/456 , H03F2200/465 , H03F2203/45112 , H03F2203/45156 , H03F2203/45292 , H03F2203/45302 , H03F2203/45481 , H03G1/04 , H03G3/3036 , H04B17/21
Abstract: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.
Abstract translation: 公开了具有温度补偿并且具有提高的温度精度的功率检测器。 在本公开的一个方面,通过改变功率检测器内的MOS晶体管的栅极和漏极电压来降低功率检测器的增益随温度的变化。 在示例性设计中,一种装置包括至少一个MOS晶体管,其接收输入信号,基于功率检测增益来检测输入信号的功率,并提供表示输入信号功率的输出信号。 至少一个MOS晶体管被施加可变栅极偏置电压和可变漏极偏置电压,以便减小功率检测增益随温度的变化。 至少一个附加MOS晶体管可以接收第二可变栅极偏置电压,并为至少一个MOS晶体管提供可变漏极偏置电压。
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公开(公告)号:US11323079B2
公开(公告)日:2022-05-03
申请号:US16804929
申请日:2020-02-28
Applicant: QUALCOMM Incorporated
Inventor: Jing-Hwa Chen , Junzhi Yu , Yan Kit Gary Hau , Guoqing Fu , Xinwei Wang , Xiangdong Zhang
Abstract: Certain aspects of the present disclosure are directed to an amplifier. The amplifier may include a transistor coupled to an output of the amplifier, and a resonator coupled between the output of the amplifier and a reference potential node, a resonant frequency of the resonator being set to be at a subharmonic of a fundamental frequency of the amplifier, and an impedance of the resonator being greater than a load impedance of the amplifier at the fundamental frequency of the amplifier.
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29.
公开(公告)号:US10381988B2
公开(公告)日:2019-08-13
申请号:US15706242
申请日:2017-09-15
Applicant: QUALCOMM Incorporated
Inventor: Yanjie Sun , Jing-Hwa Chen , Zhenying Luo , Yan Kit Gary Hau , Jisun Ryu , Ashwin Duggal , Kihun Chang , ZhenQi Chen , Xinwei Wang , Xiangdong Zhang
Abstract: Certain aspects of the present disclosure provide methods and apparatus for operating a power amplifier. In one example, the apparatus includes a power amplifier configured to amplify an input signal having a frequency to produce a radio frequency (RF) output signal at an output and a harmonic tuning circuit coupled between a power supply and the power amplifier output, the harmonic tuning circuit configured to reduce a current or voltage provided to the power amplifier via a resonance at one or more harmonics of the frequency of the input signal.
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公开(公告)号:US20180048270A1
公开(公告)日:2018-02-15
申请号:US15349225
申请日:2016-11-11
Applicant: QUALCOMM INCORPORATED
Inventor: Tianzuo Xi , Haichuan Kang , ZhenQi Chen , Zhenying Luo , Xiangdong Zhang , Xinwei Wang , Yanjie Sun , Yan Kit Gary Hau , Jing-Hwa Chen
IPC: H03F1/56 , H03F3/24 , H01L29/20 , H01L29/737 , H04B1/38 , H01L23/498 , H01L23/66 , H05K1/18 , H05K1/11 , G06F1/16 , H03F3/195 , H01L23/00
CPC classification number: H03F1/565 , G06F1/1616 , G06F1/1626 , H01L23/49827 , H01L23/49844 , H01L23/66 , H01L24/06 , H01L24/46 , H01L29/20 , H01L29/737 , H01L2223/6616 , H01L2223/6655 , H01L2224/04042 , H01L2224/16225 , H01L2224/4813 , H01L2224/4911 , H01L2224/73257 , H03F3/193 , H03F3/195 , H03F3/245 , H03F2200/387 , H04B1/38 , H05K1/115 , H05K1/18 , H05K2201/10015 , H05K2201/1003 , H05K2201/10166
Abstract: A circuit including a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground.
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