公开(公告)号：US09070870B2

公开(公告)日：2015-06-30

申请号：US14219026

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L41/12 ,  H01F10/32 ,  H01F41/32

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/222 ,  H01L41/12 ,  H01L43/08 ,  H01L43/10

Abstract: Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current.

Abstract translation: 使用在MTJ上引起定向静态应变/应力以增加垂直磁各向异性的工艺和结构构造来构造部分垂直磁各向异性（PPMA）型磁性随机存取存储器单元。 因此，MTJ的开关电流降低。 在制造过程中，受控方向和/或受控幅度诱发MTJ上的定向静态应变/应力。 MTJ永久地受到预定的定向应力，并且永久地包括提供减小的开关电流的定向静态应变/应变。

公开(公告)号：US11476186B2

公开(公告)日：2022-10-18

申请号：US17081720

申请日：2020-10-27

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Gudoor Reddy ,  Samrat Sinharoy ,  Smeeta Heggond ,  Anil Kumar Koduru ,  Kamesh Medisetti ,  Seung Hyuk Kang

IPC: H01L23/522 ,  H01L27/02

Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US10811068B2

公开(公告)日：2020-10-20

申请号：US16247247

申请日：2019-01-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01F10/32 ,  G11C11/15 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

公开(公告)号：US10431734B2

公开(公告)日：2019-10-01

申请号：US15467803

申请日：2017-03-23

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Jimmy Jianan Kan ,  Peiyuan Wang ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01F10/32

Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.

公开(公告)号：US10311930B1

公开(公告)日：2019-06-04

申请号：US15946209

申请日：2018-04-05

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G06F7/58 ,  G11C11/16 ,  G11C17/02 ,  H04L9/32

Abstract: One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations is disclosed. PUF memory is configured to permanently one-time program an initial randomly generated PUF output from PUF MRAM bit cells accessed in an initial PUF read operation, to the same PUF MRAM bit cells accessed in the initial PUF read operation. In this manner, the initial PUF output is randomly generated due to process variations of the PUF MRAM bit cells to maintain an initial unpredictable memory state, but the PUF output will be reproduced for subsequent PUF read operations to the same PUF MRAM bit cells in the PUF memory array for reproducibility. The OTP of the PUF MRAM bit cells can be accomplished by applying breakdown voltage to the PUF MRAM bit cells during programming.

公开(公告)号：US10290340B1

公开(公告)日：2019-05-14

申请号：US15939484

申请日：2018-03-29

Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

Inventor： Seong-Ook Jung ,  Sara Choi ,  Hong Keun Ahn ,  Seung Hyuk Kang ,  Sungryul Kim

IPC: G11C11/16 ,  H01L43/08 ,  G11C7/06

Abstract: Aspects disclosed in the detailed description include offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation. The OC write operation sensing circuit is configured to sense when MTJ switching occurs in MRAM bit cell. In an example, the OC write operation sensing circuit includes a voltage sensing circuit and a sense amplifier. The voltage sensing circuit employs a capacitive-coupling effect so that the output voltage drops in response to MTJ switching for both logic ‘0’ and logic ‘1’ write operations. The sense amplifier has a single input and a single output node with an output voltage indicating when MTJ switching has occurred in the MRAM bit cell. A single input transistor and pull-up transistor are provided in the sense amplifier in one example to provide an offset-canceling effect.

公开(公告)号：US20190051341A1

公开(公告)日：2019-02-14

申请号：US15676957

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wah Nam Hsu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: G11C11/16

Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

公开(公告)号：US10060880B2

公开(公告)日：2018-08-28

申请号：US15266342

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G01N27/74 ,  G01R33/09 ,  B82Y25/00

CPC classification number: G01N27/745 ,  B82Y25/00 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

公开(公告)号：US20180040668A1

公开(公告)日：2018-02-08

申请号：US15241595

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Jimmy Jianan Kan ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Aspects disclosed include reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices. In one example, a width of a bottom electrode of an MTJ device is provided to be less than a width of the MTJ stack of the MTJ device. In this manner, etching of the bottom electrode may be reduced or avoided to reduce or avoid metal redeposition as a result of over-etching the MTJ device to avoid horizontal shorts between an adjacent device(s). In another example, a seed layer is embedded in a bottom electrode of the MTJ device. In this manner, the MTJ stack is reduced in height to reduce or avoid metal redeposition as a result of over-etching the MTJ device. In another example, an MTJ device includes an embedded seed layer in a bottom electrode which also has a width less than a width of the MTJ stack.