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21.发明授权Frequency generating system, voltage-controlled oscillator module and method for adjusting signal frequency 有权频率发生系统，压控振荡器模块及调整信号频率的方法公开(公告)号：US08773209B2
公开(公告)日：2014-07-08
申请号：US13646744
申请日：2012-10-08
Applicant: Phison Electronics Corp.
Inventor： Wei-Yung Chen
IPC: H03K3/03
CPC classification number: H03L7/18 , H03L7/089 , H03L2207/06
Abstract: A voltage controlled oscillator module including a VCO unit and a gain adjustment unit is provided. The VCO unit is configured to generate a frequency signal based on a control voltage. The gain adjustment unit is coupled to the VCO unit and configured to receive a first adjustment voltage, a second adjustment voltage, and a reference voltage and accordingly adjusts the control voltage to adjust a frequency value of the frequency signal. The gain adjustment unit includes an adjustment circuit unit and a reference circuit unit. A first voltage-frequency curve of the frequency value of the frequency signal and a voltage value of the first adjustment voltage changes in response to a structure characteristic of the adjustment circuit unit. Furthermore, a frequency generating system and a method for adjusting a signal frequency of the VCO module are provided.
Abstract translation: 提供了包括VCO单元和增益调节单元的压控振荡器模块。 VCO单元被配置为基于控制电压产生频率信号。 增益调整单元耦合到VCO单元并且被配置为接收第一调整电压，第二调整电压和参考电压，并且因此调整控制电压以调整频率信号的频率值。 增益调整单元包括调整电路单元和参考电路单元。 频率信号的频率值和第一调整电压的电压值的第一电压 - 频率曲线响应于调整电路单元的结构特性而改变。 此外，提供了用于调整VCO模块的信号频率的频率产生系统和方法。
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公开(公告)号：US10403365B2
公开(公告)日：2019-09-03
申请号：US15452742
申请日：2017-03-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Shin Chang , Wei-Yung Chen
Abstract: An exemplary embodiment of the disclosure provides a switch module which includes a first conductive unit, a first switch unit and a first electrostatic protection module. The first electrostatic protection module is coupled between the first conductive unit and the first switch unit. The first electrostatic protection module includes a first protection circuit and a first inductor circuit. The first inductor circuit includes a first inductor unit, and the first inductor circuit is coupled between the first protection circuit and the first conductive unit. Accordingly, the transmission efficiency of the switch (or multiplexer) for high speed signal can be improved.
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公开(公告)号：US10297297B2
公开(公告)日：2019-05-21
申请号：US14578471
申请日：2014-12-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen
Abstract: A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.
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公开(公告)号：US09893912B1
公开(公告)日：2018-02-13
申请号：US15493139
申请日：2017-04-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Ting Wei , Wei-Yung Chen , Chao-Hsin Lin , Chih-Ming Chen
CPC classification number: H04L27/2614 , H04L25/03019 , H04L27/01
Abstract: An exemplary embodiment provides an equalizer adjustment method. The method includes: performing a handshake operation to establish a connection with a host system by a memory storage device; in the handshake operation, receiving a first signal from the host system and performing a first modulation on the first signal by the adaptive equalizer; after the handshake operation is ended, receiving a second signal from the host system and performing a second modulation on the second signal according to a modulation result of the first modulation by the adaptive equalizer to compensate the second signal; and adjusting the adaptive equalizer according to a modulation result of the second modulation.
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公开(公告)号：US09836121B2
公开(公告)日：2017-12-05
申请号：US14856563
申请日：2015-09-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen , Yu-An Chen
Abstract: An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.
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Patent Agency Ranking
公开(公告)号：US09716506B2
公开(公告)日：2017-07-25
申请号：US15261877
申请日：2016-09-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Yung Chen , Yu-Chiang Liao
CPC classification number: H03L7/091 , G11C7/1084 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0802 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/1072 , H03L7/22 , H04L7/0004 , H04L7/033
Abstract: A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.
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27.发明申请EYE-WIDTH DETECTOR, MEMORY STORAGE DEVICE AND EYE-WIDTH DETECTION METHOD OF DATA SIGNAL 有权眼睛宽度检测器，存储器件和数据信号的眼睛宽度检测方法公开(公告)号：US20170031436A1
公开(公告)日：2017-02-02
申请号：US14856563
申请日：2015-09-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen , Yu-An Chen
IPC: G06F3/01
Abstract: An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.
Abstract translation: 提供了眼宽检测器，存储器存储装置和数据信号的眼宽检测方法。 眼宽检测器包括相位插值器，校准电路和眼睛宽度检测电路。 相位插值器接收第一时钟信号和相位控制信号并输出第二时钟信号。 校准电路接收第一时钟信号和第二时钟信号并输出第一控制信号。 眼宽检测电路接收数据信号，第一时钟信号和第二时钟信号，并产生第一采样值和第二采样值。 如果第一采样值和第二采样值与第一条件不匹配，则眼宽检测电路输出第二控制信号; 否则输出数据信号的眼宽信息。 因此，可以提高眼宽检测的效率。
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公开(公告)号：US20170019116A1
公开(公告)日：2017-01-19
申请号：US15261878
申请日：2016-09-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Yung Chen , Yu-Chiang Liao
IPC: H03L7/091
CPC classification number: H03L7/091 , G11C7/1084 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0802 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/1072 , H03L7/22 , H04L7/0004 , H04L7/033
Abstract: A clock and data recovery circuit module and a phase lock method are provided. The module includes a phase detection circuit, a converter circuit and a voltage control oscillation circuit. The phase detection circuit is configured to detect a phase difference between a data signal and a feedback clock. The converter circuit is coupled to the phase detection circuit and configured to output a first phase control voltage and a second phase control voltage according to the phase difference. The voltage control oscillation circuit is coupled to the converter circuit and configured to receive the first phase control voltage and the second phase control voltage and output the feedback clock according to the first phase control voltage and the second phase control voltage.
Abstract translation: 提供时钟和数据恢复电路模块和锁相方法。 该模块包括相位检测电路，转换器电路和电压控制振荡电路。 相位检测电路被配置为检测数据信号和反馈时钟之间的相位差。 转换器电路耦合到相位检测电路，并被配置为根据相位差输出第一相位控制电压和第二相位控制电压。 电压控制振荡电路耦合到转换器电路，并被配置为接收第一相位控制电压和第二相位控制电压，并根据第一相位控制电压和第二相位控制电压输出反馈时钟。
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公开(公告)号：US09036685B2
公开(公告)日：2015-05-19
申请号：US14061762
申请日：2013-10-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Yung Chen
CPC classification number: G06F1/06 , G06F12/0246 , G06F13/16 , H03L1/02 , H03L7/00 , H04L7/0029 , H04L7/033 , H04L7/0331
Abstract: A connecting interface unit and a memory storage device without a crystal oscillator are provided and include following circuits. A phase detector detects a phase difference between a first reference signal and an input signal from a host system to generate a phase signal. A signal detecting circuit detects a signal character difference between the input signal and the first reference signal for a signal generating circuit to generate a second reference signal. A phase interpolator generates a clock signal according to the phase signal and the second reference signal. A sampling circuit generates an input data signal according to the clock signal. A transmitter circuit modulates an output data signal according to the clock signal or the second reference signal to generate an output signal, and transmits it to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission standard.
Abstract translation: 提供了连接接口单元和没有晶体振荡器的存储器，并且包括以下电路。 相位检测器检测第一参考信号和来自主机系统的输入信号之间的相位差，以产生相位信号。 信号检测电路检测用于信号发生电路的输入信号和第一参考信号之间的信号字符差异，以产生第二参考信号。 相位内插器根据相位信号和第二参考信号产生时钟信号。 采样电路根据时钟信号产生输入数据信号。 发射机电路根据时钟信号或第二参考信号对输出数据信号进行调制以产生输出信号，并将其发送到主机系统。 因此，连接接口单元符合传输标准的规范。
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公开(公告)号：US20150049849A1
公开(公告)日：2015-02-19
申请号：US14061762
申请日：2013-10-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Yung Chen
CPC classification number: G06F1/06 , G06F12/0246 , G06F13/16 , H03L1/02 , H03L7/00 , H04L7/0029 , H04L7/033 , H04L7/0331
Abstract: A connecting interface unit and a memory storage device without a crystal oscillator are provided and include following circuits. A phase detector detects a phase difference between a first reference signal and an input signal from a host system to generate a phase signal. A signal detecting circuit detects a signal character difference between the input signal and the first reference signal for a signal generating circuit to generate a second reference signal. A phase interpolator generates a clock signal according to the phase signal and the second reference signal. A sampling circuit generates an input data signal according to the clock signal. A transmitter circuit modulates an output data signal according to the clock signal or the second reference signal to generate an output signal, and transmits it to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission standard.
Abstract translation: 提供了连接接口单元和没有晶体振荡器的存储器，并且包括以下电路。 相位检测器检测第一参考信号和来自主机系统的输入信号之间的相位差，以产生相位信号。 信号检测电路检测用于信号发生电路的输入信号和第一参考信号之间的信号字符差异，以产生第二参考信号。 相位内插器根据相位信号和第二参考信号产生时钟信号。 采样电路根据时钟信号产生输入数据信号。 发射机电路根据时钟信号或第二参考信号对输出数据信号进行调制以产生输出信号，并将其发送到主机系统。 因此，连接接口单元符合传输标准的规范。
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