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公开(公告)号：US07268063B1
公开(公告)日：2007-09-11
申请号：US11141913
申请日：2005-06-01
IPC分类号： H01L21/20
CPC分类号： H01L21/02376 , H01L21/02378 , H01L21/02389 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02631 , H01L21/02636
摘要： A process is disclosed for in-situ fabricating a semiconductor component imbedded in a substrate. A substrate is ablated with a first laser beam to form a void therein. A first conductive element is formed in the void of the substrate with a second laser beam. A semiconductor material is deposited upon the first conductive element with a third laser beam operating in the presence of a depositing atmosphere. A second conductive element is formed on the first semiconductor material with a fourth laser beam. The process may be used for fabricating a Schottky barrier diode or a junction field effect transistor and the like.
摘要翻译： 公开了一种用于原位制造嵌入衬底中的半导体组件的工艺。 用第一激光束烧蚀衬底以在其中形成空隙。 第一导电元件用第二激光束形成在衬底的空隙中。 在存在沉积气氛的情况下，第三激光束在第一导电元件上沉积半导体材料。 第二导电元件用第四激光束形成在第一半导体材料上。 该工艺可用于制造肖特基势垒二极管或结型场效应晶体管等。
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公开(公告)号：US10043740B2
公开(公告)日：2018-08-07
申请号：US15208313
申请日：2016-07-12
申请人： Sri Ranga Sai Boyapati , Rahul N. Manepalli , Dilan Seneviratne , Srinivas V. Pietambaram , Kristof Darmawikarta , Robert Alan May , Islam A. Salama
发明人： Sri Ranga Sai Boyapati , Rahul N. Manepalli , Dilan Seneviratne , Srinivas V. Pietambaram , Kristof Darmawikarta , Robert Alan May , Islam A. Salama
IPC分类号： H01L23/48 , H01L23/498 , H01L21/02 , H01L21/48 , H01L23/00 , H01L25/065
摘要： Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
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23.发明申请METHOD OF PROVIDING A PRINTED CIRCUIT BOARD USING LASER ASSISTED METALLIZATION AND PATTERNING OF A MICROELECTRONIC SUBSTRATE 审中-公开使用激光辅助金属化和微电子基板图案提供印刷电路板的方法公开(公告)号：US20160302307A1
公开(公告)日：2016-10-13
申请号：US11765204
申请日：2007-06-19
申请人： Islam A. Salama
发明人： Islam A. Salama
CPC分类号： H05K1/115 , H05K1/0296 , H05K1/09 , H05K1/181 , H05K3/0026 , H05K3/185 , H05K3/421 , H05K3/422 , H05K2201/0394 , H05K2201/09509 , H05K2201/09827 , H05K2201/10159 , H05K2203/107 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A method of providing a printed circuit board, a printed circuit board formed according to the method, and a system comprising the printed circuit board. The method comprises: providing a microelectronic substrate; providing a via-defining substrate by providing via openings in the substrate using laser irradiation; providing a laser activatable film on the via-defining substrate; and providing interconnects on the via-defining substrate. Providing interconnects comprises providing a patterned build-up layer on the via-defining substrate comprising exposing the laser activatable film to laser irradiation to selectively activate portions of the film according to a predetermined interconnect pattern; and metallizing the patterned build-up layer according to the predetermined interconnect pattern to yield the interconnects to provide the printed circuit board.
摘要翻译： 一种提供印刷电路板的方法，根据该方法形成的印刷电路板以及包括印刷电路板的系统。 该方法包括：提供微电子衬底; 通过使用激光照射在所述衬底中提供通路孔来提供通孔限定衬底; 在通孔限定衬底上提供激光可激活膜; 并在通孔限定衬底上提供互连。 提供互连包括在通孔限定衬底上提供图案化的构建层，包括将激光可激活膜暴露于激光照射以根据预定的互连图案选择性地激活膜的部分; 以及根据预定的互连图案对图案化的堆积层进行金属化以产生互连以提供印刷电路板。
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公开(公告)号：US20140168032A1
公开(公告)日：2014-06-19
申请号：US13715193
申请日：2012-12-14
申请人： Johanna Swan , Uygar Avci , Islam A. Salama , Ravi Pallarisetty
发明人： Johanna Swan , Uygar Avci , Islam A. Salama , Ravi Pallarisetty
CPC分类号： G06F3/1446 , G02F1/13336 , G02F1/1345 , G09F9/3026 , G09F9/35 , G09G3/20 , G09G5/003 , G09G5/14 , G09G2300/026 , G09G2320/02 , G09G2340/14 , G09G2360/04 , H01L27/3293
摘要： Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive circuitry can be removably coupled with a display device via an array of contact members. The display device can include image-producing elements or pixels that can be selectively driven by the backpanel device via corresponding portions of the array of contact members. Multiple display devices can be disposed adjacently on one or more backpanel devices such that an image displayed across the multiple display devices appears seamless.
摘要翻译： 这里通常描述无缝显示器的系统和方法的实施例。 在一些实施例中，包括显示器驱动电路的背板装置可以通过接触构件阵列可移除地与显示装置耦合。 显示装置可以包括图像产生元件或可以由背板装置通过接触构件阵列的相应部分选择性地驱动的图像。 多个显示设备可以相邻地布置在一个或多个背板设备上，使得跨越多个显示设备显示的图像看起来是无缝的。
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公开(公告)号：US08450857B2
公开(公告)日：2013-05-28
申请号：US13526434
申请日：2012-06-18
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/49816 , H01L24/13 , H01L2224/16225 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.
摘要翻译： 描述了通过聚合物块中的通孔形成集成电路芯片封装的方法，以及这些封装。 例如，第一互连层可以形成在模制的聚合物嵌段上，其中第一互连层包括通过第一聚合物层和嵌段的第一互连。 然后，可以在第一互连层上形成至少一个第二互连层，其中第二互连层包括通过第二聚合物层和第一互连层的第一互连的第二互连。 然后可以通过模具通孔形成通孔，进入第一互连层和第一互连。 穿通模具通孔可以填充有焊料，以形成与第一互连件接触并在块体上方延伸的凸块。 还描述和要求保护其他实施例。
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公开(公告)号：US20120299179A1
公开(公告)日：2012-11-29
申请号：US13526434
申请日：2012-06-18
IPC分类号： H01L23/522 , H01L21/78 , H01L21/768
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/49816 , H01L24/13 , H01L2224/16225 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be farmed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.
摘要翻译： 描述了通过聚合物块中的通孔形成集成电路芯片封装的方法，以及这些封装。 例如，第一互连层可以形成在模制的聚合物嵌段上，其中第一互连层包括通过第一聚合物层和嵌段的第一互连。 然后，可以在第一互连层上形成至少一个第二互连层，其中第二互连层包括通过第二聚合物层和第一互连层的第一互连的第二互连。 然后通过模具通孔可以通过块进入农场，进入第一互连层和第一互连。 穿通模具通孔可以填充有焊料，以形成与第一互连件接触并在块体上方延伸的凸块。 还描述和要求保护其他实施例。
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公开(公告)号：US08080836B2
公开(公告)日：2011-12-20
申请号：US11825809
申请日：2007-07-09
IPC分类号： H01L21/02
CPC分类号： H01L21/02376 , H01L21/02378 , H01L21/02389 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02631 , H01L21/02636
摘要： A process is disclosed for in-situ fabricating a semiconductor component imbedded in a substrate. A substrate is ablated with a first laser beam to form a void therein. A first conductive element is formed in the void of the substrate with a second laser beam. A semiconductor material is deposited upon the first conductive element with a third laser beam operating in the presence of a depositing atmosphere. A second conductive element is formed on the first semiconductor material with a fourth laser beam. The process may be used for fabricating a Schottky barrier diode or a junction field effect transistor and the like.
摘要翻译： 公开了一种用于原位制造嵌入衬底中的半导体组件的工艺。 用第一激光束烧蚀衬底以在其中形成空隙。 第一导电元件用第二激光束形成在衬底的空隙中。 在存在沉积气氛的情况下，第三激光束在第一导电元件上沉积半导体材料。 第二导电元件用第四激光束形成在第一半导体材料上。 该工艺可用于制造肖特基势垒二极管或结型场效应晶体管等。
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公开(公告)号：US20170131556A1
公开(公告)日：2017-05-11
申请号：US14938194
申请日：2015-11-11
摘要： A method includes generating a laser beam and applying the beam to a substrate to form a via in the substrate. The laser beam has an intensity profile taken at a cross-section transverse to the direction of propagation of the beam. The intensity profile has a first substantially uniform level across an interior region of the cross-section and a second substantially uniform level across an exterior region of the cross-section. The second intensity level is greater than the first intensity level.
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公开(公告)号：US09211609B2
公开(公告)日：2015-12-15
申请号：US11319824
申请日：2005-12-28
IPC分类号： B23K26/00 , B23K26/38 , B23K26/073 , H01L21/311 , H05K3/00 , B23K26/40
CPC分类号： B23K26/386 , B23K26/0734 , B23K26/382 , B23K26/389 , B23K26/40 , B23K26/402 , B23K2101/40 , B23K2103/30 , B23K2103/50 , B23K2103/52 , H01L21/31138 , H05K3/0026
摘要： A method includes generating a laser beam and applying the beam to a substrate to form a via in the substrate. The laser beam has an intensity profile taken at a cross-section transverse to the direction of propagation of the beam. The intensity profile has a first substantially uniform level across an interior region of the cross-section and a second substantially uniform level across an exterior region of the cross-section. The second intensity level is greater than the first intensity level.
摘要翻译： 一种方法包括产生激光束并将光束施加到衬底以在衬底中形成通孔。 激光束具有在横向于横梁的传播方向的横截面处获得的强度分布。 强度分布在横截面的内部区域上具有第一基本上均匀的水平，并且横跨横截面的外部区域具有第二基本均匀的水平。 第二强度水平大于第一强度水平。
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公开(公告)号：US08278214B2
公开(公告)日：2012-10-02
申请号：US12646836
申请日：2009-12-23
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/49816 , H01L24/13 , H01L2224/16225 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.
摘要翻译： 描述了通过聚合物块中的通孔形成集成电路芯片封装的方法，以及这些封装。 例如，第一互连层可以形成在模制的聚合物嵌段上，其中第一互连层包括通过第一聚合物层和嵌段的第一互连。 然后，可以在第一互连层上形成至少一个第二互连层，其中第二互连层包括通过第二聚合物层和第一互连层的第一互连的第二互连。 然后可以通过模具通孔形成通孔，进入第一互连层和第一互连。 穿通模具通孔可以填充有焊料，以形成与第一互连件接触并在块体上方延伸的凸块。 还描述和要求保护其他实施例。
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