公开(公告)号：US12087691B2

公开(公告)日：2024-09-10

申请号：US17480531

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Veeraraghavan S. Basker ,  Lawrence A. Clevenger ,  Nicolas Loubet ,  Dechao Guo ,  Kisik Choi ,  Kangguo Cheng ,  Carl Radens

IPC: H01L27/088 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

公开(公告)号：US20240107900A1

公开(公告)日：2024-03-28

申请号：US17934212

申请日：2022-09-22

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Carl Radens ,  Ching-Tzu Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1675

Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

公开(公告)号：US20240008242A1

公开(公告)日：2024-01-04

申请号：US17854780

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Carl Radens ,  Albert M. Chu ,  Brent A. Anderson ,  Junli Wang ,  Julien Frougier ,  Ravikumar Ramachandran

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

公开(公告)号：US11690305B2

公开(公告)日：2023-06-27

申请号：US17303836

申请日：2021-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Carl Radens ,  Juntao Li

IPC: H10N70/00 ,  G11C13/00

CPC classification number: H10N70/841 ,  G11C13/0004 ,  H10N70/011 ,  H10N70/8265 ,  H10N70/8825 ,  H10N70/8828

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

公开(公告)号：US11683998B2

公开(公告)日：2023-06-20

申请号：US17207798

申请日：2021-03-22

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Carl Radens ,  Ruilong Xie

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/82 ,  H10B63/84 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/8265 ,  H10N70/841

Abstract: A semiconductor structure for a vertical phase change memory cell that includes a bottom electrode on a portion of a semiconductor substrate and a pair of vertical phase change bridge elements that are each on a portion of the bottom electrode. The semiconductor structure for the vertical phase change memory cell includes a dielectric material separating the pair of vertical phase change bridge elements and a top electrode over the pair of vertical phase change bridge elements.

公开(公告)号：US20230079751A1

公开(公告)日：2023-03-16

申请号：US17472759

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  JUNTAO LI ,  Carl Radens

IPC: H01L27/092 ,  H01L21/8238

Abstract: An approach provides a semiconductor structure for a first device with a first plurality of channels with a larger horizontal dimension than a vertical dimension of the first plurality of channels a second device comprising a second plurality of channels with a smaller horizontal dimension than the vertical dimension of the second plurality of channels. The first plurality of channels and the second plurality of channels have a same channel width in embodiments of the present invention. The first device is an n-type horizontal gate-all-around device and the second device is a p-type horizontal gate-all-around device.

公开(公告)号：US11588104B2

公开(公告)日：2023-02-21

申请号：US17346686

申请日：2021-06-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  Ruilong Xie ,  Juntao Li

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.

公开(公告)号：US11251288B2

公开(公告)日：2022-02-15

申请号：US16876443

申请日：2020-05-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Juntao Li ,  Dechao Guo ,  Tao Li ,  Tsung-Sheng Kang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

公开(公告)号：US20210311874A1

公开(公告)日：2021-10-07

申请号：US16838294

申请日：2020-04-02

Applicant: International Business Machines Corporation

Inventor： Ahmet Serkan Ozcan ,  Tomasz Kornuta ,  Carl Radens ,  Nicolas Antoine

IPC: G06F12/0817 ,  G06F12/02 ,  G06F16/33 ,  G11C11/4093 ,  G11C11/4076 ,  G06N3/063

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

公开(公告)号：US11024551B1

公开(公告)日：2021-06-01

申请号：US16735857

申请日：2020-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Somnath Ghosh ,  Carl Radens

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A method is presented for forming a multi-level of interconnects underneath a complementary metal oxide semiconductor (CMOS) device. The method includes forming a stack including alternating layers of a semiconductor material and a first conductive material, patterning vias in the stack to define multiple stacks, depositing a first block material within each of the vias, forming a series of first block materials within a first via, forming a series of second block materials within a second via, the first and second vias being on opposed ends of a stack of the multiple stacks, and performing vertical metallization between the first block material and the series of first block materials in the first via, and between the first block material and the series of second block materials in the second via.